On Fri, Apr 25, 2025 at 1:02 PM Philippe Mathieu-Daudé
wrote:
>
> On 25/4/25 12:55, Paolo Bonzini wrote:
> > On Thu, Apr 24, 2025 at 4:39 PM Paolo Bonzini wrote:
> >>> Thanks!
> >>>
> >>> Applied to riscv-to-apply.next
> >>
> >> As Daniel noticed, I was expecting
> >> https://lore.kernel.org/qemu
On 25/4/25 12:55, Paolo Bonzini wrote:
On Thu, Apr 24, 2025 at 4:39 PM Paolo Bonzini wrote:
Thanks!
Applied to riscv-to-apply.next
As Daniel noticed, I was expecting
https://lore.kernel.org/qemu-devel/20250210133134.90879-1-phi...@linaro.org/
to get in before this series.
If you need a vers
On Thu, Apr 24, 2025 at 4:39 PM Paolo Bonzini wrote:
> > Thanks!
> >
> > Applied to riscv-to-apply.next
>
> As Daniel noticed, I was expecting
> https://lore.kernel.org/qemu-devel/20250210133134.90879-1-phi...@linaro.org/
> to get in before this series.
>
> If you need a version that applies witho
On 4/24/25 03:26, Alistair Francis wrote:
On Sun, Apr 6, 2025 at 5:03 PM Paolo Bonzini wrote:
This is the combination of the previously posted series to store max SATP
mode in RISCVCPUConfig as a single integer, and convert CPU definitions
to a small extension of RISCVCPUConfig called RISCVCPU
On Sun, Apr 6, 2025 at 5:03 PM Paolo Bonzini wrote:
>
> This is the combination of the previously posted series to store max SATP
> mode in RISCVCPUConfig as a single integer, and convert CPU definitions
> to a small extension of RISCVCPUConfig called RISCVCPUDef. I put them
> together because th
This is the combination of the previously posted series to store max SATP
mode in RISCVCPUConfig as a single integer, and convert CPU definitions
to a small extension of RISCVCPUConfig called RISCVCPUDef. I put them
together because the first part (patches 1-6) is already acked/reviewed.
As menti
