After some investigation on this, I found that even faking ctr_el0
content does not work. Indeed, "dc cvau" and "ic ivau" both are
privileged too (and fail with illegal instruction).
I started looking how other projects are handling this. In the case of
firefox js engine, they simply perform a
On 2/15/23 02:49, Pierrick Bouvier wrote:
I'm not an expert on this area, but I imagine that booting a full VM will force TCG to
emit code at the same address twice (after having generated enough translated blocks),
which shows that generic flush_idcache_range works. Is that reasoning correct?
On 2/14/23 17:44, Peter Maydell wrote:
On Mon, 13 Feb 2023 at 20:50, Pierrick Bouvier
wrote:
mrs instruction fails as an illegal instruction.
For now, no cache information is retrieved for this platform.
It could be specialized later, using Windows API.
Unless I'm misreading the code, there'
On 2/14/23 06:44, Peter Maydell wrote:
This will cause us to not use the generic aarch64 flush_idcache_range(),
which uses DC CVAU and IC IVAU. Does that not work on Windows?
If it doesn't then I think the ifdeffery would be more clearly
structured as
#elif defined(__aarch64__)
ifdef CONFIG_DA
On Mon, 13 Feb 2023 at 20:50, Pierrick Bouvier
wrote:
>
> mrs instruction fails as an illegal instruction.
> For now, no cache information is retrieved for this platform.
> It could be specialized later, using Windows API.
Unless I'm misreading the code, there's a sys_cache_info()
implementation
mrs instruction fails as an illegal instruction.
For now, no cache information is retrieved for this platform.
It could be specialized later, using Windows API.
Signed-off-by: Pierrick Bouvier
---
util/cacheflush.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/util/cac
