On 2/16/24 03:13, Alvin Chang wrote:
The RISC-V debug specification defines an optional CSR "tcontrol" within
the trigger module. This commit adds its read/write operations and
related bit-field definitions.
Signed-off-by: Alvin Chang
---
Reviewed-by: Daniel Henrique Barboza
target/ri
;
liwei1...@gmail.com; zhiwei_...@linux.alibaba.com
Subject: Re: [PATCH 1/4] target/riscv: Add CSR tcontrol of debug trigger module
On 2/16/24 03:13, Alvin Chang wrote:
The RISC-V debug specification defines an optional CSR "tcontrol"
within the trigger module. This commit adds its
..@gmail.com; zhiwei_...@linux.alibaba.com
> Subject: Re: [PATCH 1/4] target/riscv: Add CSR tcontrol of debug trigger
> module
>
>
>
> On 2/16/24 03:13, Alvin Chang wrote:
> > The RISC-V debug specification defines an optional CSR "tcontrol"
> > within the trigger modul
On 2/16/24 03:13, Alvin Chang wrote:
The RISC-V debug specification defines an optional CSR "tcontrol" within
the trigger module. This commit adds its read/write operations and
related bit-field definitions.
Signed-off-by: Alvin Chang
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_b
The RISC-V debug specification defines an optional CSR "tcontrol" within
the trigger module. This commit adds its read/write operations and
related bit-field definitions.
Signed-off-by: Alvin Chang
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 3 +++
target/riscv/csr.c | 15
