On 3/12/25 07:18, Peter Maydell wrote:
On Mon, 10 Mar 2025 at 20:36, Joe Komlodi wrote:
On ARM hosts with CTR_EL0.DIC and CTR_EL0.IDC set, this would only cause
an ISB to be executed during cache maintenance, which could lead to QEMU
executing TBs containing garbage instructions.
This seems t
On Mon, 10 Mar 2025 at 20:36, Joe Komlodi wrote:
>
> On ARM hosts with CTR_EL0.DIC and CTR_EL0.IDC set, this would only cause
> an ISB to be executed during cache maintenance, which could lead to QEMU
> executing TBs containing garbage instructions.
>
> This seems to be because the ISB finishes ex
On ARM hosts with CTR_EL0.DIC and CTR_EL0.IDC set, this would only cause
an ISB to be executed during cache maintenance, which could lead to QEMU
executing TBs containing garbage instructions.
This seems to be because the ISB finishes executing instructions and
flushes the pipeline, but the ISB do
