Re: [PATCH 1/1] target/riscv: Not allow write mstatus_vs without RVV

On Fri, Dec 15, 2023 at 12:34 PM LIU Zhiwei wrote: > > If CPU does not implement the Vector extension, it usually means > mstatus vs hardwire to zero. So we should not allow write a > non-zero value to this field. > > Signed-off-by: LIU Zhiwei Thanks! Applied to riscv-to-apply.next Alistair >

Re: [PATCH 1/1] target/riscv: Not allow write mstatus_vs without RVV

On Fri, Dec 15, 2023 at 12:34 PM LIU Zhiwei wrote: > > If CPU does not implement the Vector extension, it usually means > mstatus vs hardwire to zero. So we should not allow write a > non-zero value to this field. > > Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Alistair > --- > t

[PATCH 1/1] target/riscv: Not allow write mstatus_vs without RVV

If CPU does not implement the Vector extension, it usually means mstatus vs hardwire to zero. So we should not allow write a non-zero value to this field. Signed-off-by: LIU Zhiwei --- target/riscv/csr.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b