On Fri, 25 Oct 2019 at 10:08, Christophe Lyon
wrote:
>
> This is derived from cortex-m4 description, adding DP support and FPv5
> instructions with the corresponding flags in isar and mvfr2.
>
> Checked that it could successfully execute
> vrinta.f32 s15, s15
> while cortex-m4 emulation rejects it
On Tue, 5 Nov 2019 at 21:23, Peter Maydell wrote:
>
> On Mon, 4 Nov 2019 at 16:41, Christophe Lyon
> wrote:
> >
> > ping?
>
> This is on my list to review, but it's missed softfreeze so
> as a new feature it will go into 5.0 once trunk reopens for
> development at the end of the year, so it's no
On Mon, 4 Nov 2019 at 16:41, Christophe Lyon wrote:
>
> ping?
This is on my list to review, but it's missed softfreeze so
as a new feature it will go into 5.0 once trunk reopens for
development at the end of the year, so it's not the
highest priority for patch review for me I'm afraid.
thanks
--
Christophe Lyon writes:
> This is derived from cortex-m4 description, adding DP support and FPv5
> instructions with the corresponding flags in isar and mvfr2.
>
> Checked that it could successfully execute
> vrinta.f32 s15, s15
> while cortex-m4 emulation rejects it with "illegal instruction".
ping?
http://patchwork.ozlabs.org/patch/1183934/
On Fri, 25 Oct 2019 at 11:08, Christophe Lyon
wrote:
>
> This is derived from cortex-m4 description, adding DP support and FPv5
> instructions with the corresponding flags in isar and mvfr2.
>
> Checked that it could successfully execute
> vrinta.
This is derived from cortex-m4 description, adding DP support and FPv5
instructions with the corresponding flags in isar and mvfr2.
Checked that it could successfully execute
vrinta.f32 s15, s15
while cortex-m4 emulation rejects it with "illegal instruction".
Signed-off-by: Christophe Lyon
---
