Hi Alistair,
On Mon, Sep 9, 2024 at 10:32 AM Alistair Francis wrote:
>
> On Thu, Aug 8, 2024 at 6:21 PM Yong-Xuan Wang
> wrote:
> >
> > The section 4.5.2 of the RISC-V AIA specification says that any write
> > to a sourcecfg register of an APLIC might (or might not) cause the
> > corresponding
On Thu, Aug 8, 2024 at 6:21 PM Yong-Xuan Wang wrote:
>
> The section 4.5.2 of the RISC-V AIA specification says that any write
> to a sourcecfg register of an APLIC might (or might not) cause the
> corresponding interrupt-pending bit to be set to one if the rectified
> input value is high (= 1) un
The section 4.5.2 of the RISC-V AIA specification says that any write
to a sourcecfg register of an APLIC might (or might not) cause the
corresponding interrupt-pending bit to be set to one if the rectified
input value is high (= 1) under the new source mode.
If an interrupt is asserted before the
