Re: [PATCH 1/1] Add Zihintpause support

Am Dienstag, 10. Mai 2022, 08:42:31 CEST schrieb Dao Lu: > Added support for RISC-V PAUSE instruction from Zihintpause extension, enabeld > by default. > > Signed-off-by: Dao Lu This patch with your fixup applied to it and of course a matching kernel: Tested-by: Heiko Stuebner > --- > targe

Re: [PATCH 1/1] Add Zihintpause support

Thanks Richard! I have fixed it following your advice: diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 528c30c9a2..acd2548e9b 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -808,9 +808,13 @@

Re: [PATCH 1/1] Add Zihintpause support

On 5/9/22 23:42, Dao Lu wrote: +static bool trans_pause(DisasContext *ctx, arg_pause *a) +{ +REQUIRE_ZIHINTPAUSE(ctx); + +/* + * PAUSE is a no-op in QEMU, + * however we need to clear the reservation + */ +tcg_gen_movi_tl(load_res, -1); I recommend ending the TB and retu

[PATCH 1/1] Add Zihintpause support

Added support for RISC-V PAUSE instruction from Zihintpause extension, enabeld by default. Signed-off-by: Dao Lu --- target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn32.decode | 7 ++- target/riscv/insn_trans/tran