[PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode

From: Ian Brockbank The new CLIC interrupt-handling mode is encoded as a new state in the existing WARL xtvec register, where the low two bits of are 11. Signed-off-by: LIU Zhiwei Signed-off-by: Ian Brockbank --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 2 ++ target/riscv/c

Re: [RFC PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode

LIU Zhiwei 於 2021年4月9日 週五 下午3:51寫道： > The new CLIC interrupt-handling mode is encoded as a new state in the > existing WARL xtvec register, where the low two bits of are 11. > > Signed-off-by: LIU Zhiwei > --- > target/riscv/csr.c | 22 -- > 1 file changed, 20 insertions(+),

Re: [RFC PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode

LIU Zhiwei 於 2021年4月9日 週五 下午3:51寫道： > The new CLIC interrupt-handling mode is encoded as a new state in the > existing WARL xtvec register, where the low two bits of are 11. > > Signed-off-by: LIU Zhiwei > --- > target/riscv/csr.c | 22 -- > 1 file changed, 20 insertions(+),

[RFC PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode

The new CLIC interrupt-handling mode is encoded as a new state in the existing WARL xtvec register, where the low two bits of are 11. Signed-off-by: LIU Zhiwei --- target/riscv/csr.c | 22 -- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/