On 9/12/22 00:03, Paolo Bonzini wrote:
+/* five rows for no prefix, 66, F3, F2, 66+F2 */
+static X86OpEntry opcodes_0F38_F0toFF[16][5] = {
const.
r~
On 9/12/22 00:03, Paolo Bonzini wrote:
+case X86_TYPE_B: /* VEX. selects a GPR */
+op->unit = X86_OP_INT;
+op->n = s->vex_v;
+break;
Could use a comment for where missing vex prefix is diagnosed.
I guess it's one of the "vexN" group markers in the insn table?
The new decoder is based on three principles:
- use mostly table-driven decoding, using tables derived as much as possible
from the Intel manual. Centralizing the decode the operands makes it
more homogeneous, for example all immediates are signed. All modrm
handling is in one function, an
