[PATCH 04/11] target/riscv: Update CSR xie in CLIC mode

From: Ian Brockbank The xie CSR appears hardwired to zero in CLIC mode, replaced by separate memory-mapped interrupt enables (clicintie[i]). Writes to xie will be ignored and will not trap (i.e., no access faults). Signed-off-by: LIU Zhiwei Signed-off-by: Ian Brockbank --- target/riscv/csr.c

Re: [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode

LIU Zhiwei 於 2021年4月9日 週五 下午3:51寫道： > The xie CSR appears hardwired to zero in CLIC mode, replaced by separate > memory-mapped interrupt enables (clicintie[i]). Writes to xie will be > ignored and will not trap (i.e., no access faults). > > Signed-off-by: LIU Zhiwei > --- > target/riscv/csr.c |

[RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode

The xie CSR appears hardwired to zero in CLIC mode, replaced by separate memory-mapped interrupt enables (clicintie[i]). Writes to xie will be ignored and will not trap (i.e., no access faults). Signed-off-by: LIU Zhiwei --- target/riscv/csr.c | 19 --- 1 file changed, 16 inserti