On Mon, 7 Jun 2021 at 22:19, Richard Henderson
wrote:
>
> On 6/7/21 9:57 AM, Peter Maydell wrote:
> > @@ -410,16 +415,19 @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env)
> > env->v7m.fpccr[is_secure] &= ~R_V7M_FPCCR_LSPACT_MASK;
> >
> > if (ts) {
> > -/* Clear s0 to s31
On 6/7/21 9:57 AM, Peter Maydell wrote:
@@ -410,16 +415,19 @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env)
env->v7m.fpccr[is_secure] &= ~R_V7M_FPCCR_LSPACT_MASK;
if (ts) {
-/* Clear s0 to s31 and the FPSCR */
+/* Clear s0 to s31 and the FPSCR and VPR */
When MVE is supported, the VPR register has a place on the exception
stack frame in a previously reserved slot just above the FPSCR.
It must also be zeroed in various situations when we invalidate
FPU context.
Update the code which handles the stack frames (exception entry and
exit code, VLLDM, an
