[PATCH 01/11] target/riscv: Add CLIC CSR mintstatus

2024-08-14 Thread Ian Brockbank
From: Ian Brockbank CSR mintstatus holds the active interrupt level for each supported privilege mode. sintstatus, and user, uintstatus, provide restricted views of mintstatus. Signed-off-by: Ian Brockbank Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 3 +++ target/riscv/cpu_bits.h

Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus

2021-09-28 Thread Alistair Francis
On Tue, Sep 28, 2021 at 6:10 PM Frank Chang wrote: > > On Fri, Jul 2, 2021 at 3:17 PM Alistair Francis wrote: >> >> On Fri, Jul 2, 2021 at 4:11 PM LIU Zhiwei wrote: >> > >> > >> > On 2021/7/2 下午1:38, Alistair Francis wrote: >> > > On Thu, Jul 1, 2021 at 6:45 PM Frank Chang >> > > wrote: >> > >

Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus

2021-09-28 Thread Frank Chang
On Fri, Jul 2, 2021 at 3:17 PM Alistair Francis wrote: > On Fri, Jul 2, 2021 at 4:11 PM LIU Zhiwei wrote: > > > > > > On 2021/7/2 下午1:38, Alistair Francis wrote: > > > On Thu, Jul 1, 2021 at 6:45 PM Frank Chang > wrote: > > >> LIU Zhiwei 於 2021年4月20日 週二 上午8:49寫道： > > >>> > > >>> On 2021/4/20 上

Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus

2021-07-02 Thread Alistair Francis
On Fri, Jul 2, 2021 at 4:11 PM LIU Zhiwei wrote: > > > On 2021/7/2 下午1:38, Alistair Francis wrote: > > On Thu, Jul 1, 2021 at 6:45 PM Frank Chang wrote: > >> LIU Zhiwei 於 2021年4月20日 週二 上午8:49寫道： > >>> > >>> On 2021/4/20 上午7:23, Alistair Francis wrote: > On Fri, Apr 9, 2021 at 5:52 PM LIU Zh

Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus

2021-07-01 Thread LIU Zhiwei
On 2021/7/2 下午1:38, Alistair Francis wrote: On Thu, Jul 1, 2021 at 6:45 PM Frank Chang wrote: LIU Zhiwei 於 2021年4月20日 週二 上午8:49寫道： On 2021/4/20 上午7:23, Alistair Francis wrote: On Fri, Apr 9, 2021 at 5:52 PM LIU Zhiwei wrote: CSR mintstatus holds the active interrupt level for each suppo

Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus

2021-07-01 Thread Alistair Francis
On Thu, Jul 1, 2021 at 6:45 PM Frank Chang wrote: > > LIU Zhiwei 於 2021年4月20日 週二 上午8:49寫道： >> >> >> On 2021/4/20 上午7:23, Alistair Francis wrote: >> > On Fri, Apr 9, 2021 at 5:52 PM LIU Zhiwei wrote: >> >> CSR mintstatus holds the active interrupt level for each supported >> >> privilege mode. si

Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus

2021-07-01 Thread LIU Zhiwei
On 2021/7/1 下午4:45, Frank Chang wrote: LIU Zhiwei mailto:zhiwei_...@c-sky.com>> 於 2021年4月20日 週二 上午8:49寫道： On 2021/4/20 上午7:23, Alistair Francis wrote: > On Fri, Apr 9, 2021 at 5:52 PM LIU Zhiwei mailto:zhiwei_...@c-sky.com>> wrote: >> CSR mintstatus holds the active interrupt leve

Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus

2021-07-01 Thread Frank Chang
LIU Zhiwei 於 2021年4月20日 週二 上午8:49寫道： > > On 2021/4/20 上午7:23, Alistair Francis wrote: > > On Fri, Apr 9, 2021 at 5:52 PM LIU Zhiwei wrote: > >> CSR mintstatus holds the active interrupt level for each supported > >> privilege mode. sintstatus, and user, uintstatus, provide restricted > >> views

Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus

2021-04-19 Thread LIU Zhiwei
On 2021/4/20 上午7:23, Alistair Francis wrote: On Fri, Apr 9, 2021 at 5:52 PM LIU Zhiwei wrote: CSR mintstatus holds the active interrupt level for each supported privilege mode. sintstatus, and user, uintstatus, provide restricted views of mintstatus. Signed-off-by: LIU Zhiwei --- target/r

Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus

2021-04-19 Thread Alistair Francis
On Fri, Apr 9, 2021 at 5:52 PM LIU Zhiwei wrote: > > CSR mintstatus holds the active interrupt level for each supported > privilege mode. sintstatus, and user, uintstatus, provide restricted > views of mintstatus. > > Signed-off-by: LIU Zhiwei > --- > target/riscv/cpu.h | 2 ++ > target/ri

[RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus

2021-04-09 Thread LIU Zhiwei
CSR mintstatus holds the active interrupt level for each supported privilege mode. sintstatus, and user, uintstatus, provide restricted views of mintstatus. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 11 +++ target/riscv/csr.c | 26 +