Re: [CAUTION - External Sender] Re: [PATCH 00/12] target/riscv: Fix some RISC-V instruction corner cases

Hi Max, On Fri, Feb 28, 2025 at 1:47 AM Max Chou wrote: > While reviewing this patchset, I noticed a few missing parts related to > the mismatched input EEWs encoding constraint. > I also found a few other rvv encoding issues and planned to submit an > upstream patchset to address them. > However

Re: [PATCH 00/12] target/riscv: Fix some RISC-V instruction corner cases

Hi Anton, I hope you’re doing well. While reviewing this patchset, I noticed a few missing parts related to the mismatched input EEWs encoding constraint. I also found a few other rvv encoding issues and planned to submit an upstream patchset to address them. However, I think it would be bette

[PATCH 00/12] target/riscv: Fix some RISC-V instruction corner cases

This series fixes some RISC-V instruction corner cases, specifically illegal overlaps between mask and source registers, illegal overlaps between source registers and illegal overlaps between source and destination registers. These were found by looking at miscompares between QEMU and the Tenstorre