On Mon, 24 Feb 2025 09:14:19 +0100
Cédric Le Goater wrote:
> > An aspect that needs attention here is whether this change in the
> > wmask and PMCSR bits becomes a problem for migration, and how we
> > might solve it. For a guest migrating old->new, the device would
> > always be in the D0 power
On 2/20/25 23:54, Michael S. Tsirkin wrote:
On Thu, Feb 20, 2025 at 03:48:53PM -0700, Alex Williamson wrote:
Eric recently identified an issue[1] where during graceful shutdown
of a VM in a vIOMMU configuration, the guest driver places the device
into the D3 power state, the vIOMMU is then disab
An aspect that needs attention here is whether this change in the
wmask and PMCSR bits becomes a problem for migration, and how we
might solve it. For a guest migrating old->new, the device would
always be in the D0 power state, but the register becomes writable.
In the opposite direction, is it
>-Original Message-
>From: Alex Williamson
>Subject: [PATCH 0/5] PCI: Implement basic PCI PM capability backing
>
>Eric recently identified an issue[1] where during graceful shutdown
>of a VM in a vIOMMU configuration, the guest driver places the device
>into th
On Thu, Feb 20, 2025 at 03:48:53PM -0700, Alex Williamson wrote:
> Eric recently identified an issue[1] where during graceful shutdown
> of a VM in a vIOMMU configuration, the guest driver places the device
> into the D3 power state, the vIOMMU is then disabled, triggering an
> AddressSpace update.
Eric recently identified an issue[1] where during graceful shutdown
of a VM in a vIOMMU configuration, the guest driver places the device
into the D3 power state, the vIOMMU is then disabled, triggering an
AddressSpace update. The device BARs are still mapped into the AS,
but the vfio host driver
