On 5/27/23 16:19, Richard Henderson wrote:
Extract some common code from Alpha and Arm, and which will
shortly also be required by the RISC-V Zfa extension.
Added a new test for Alpha; I already had a RISU test for Arm.
r~
Richard Henderson (4):
fpu: Add float64_to_int{32,64}_modulo
tes
On Sat, May 27, 2023 at 4:19 PM Richard Henderson
wrote:
>
> Extract some common code from Alpha and Arm, and which will
> shortly also be required by the RISC-V Zfa extension.
> Added a new test for Alpha; I already had a RISU test for Arm.
Thank you for providing a generic implementation of thi
On 6/21/23 11:12, Richard Henderson wrote:
On 5/27/23 16:19, Richard Henderson wrote:
Extract some common code from Alpha and Arm, and which will
shortly also be required by the RISC-V Zfa extension.
Added a new test for Alpha; I already had a RISU test for Arm.
r~
Richard Henderson (4):
On 5/27/23 16:19, Richard Henderson wrote:
Extract some common code from Alpha and Arm, and which will
shortly also be required by the RISC-V Zfa extension.
Added a new test for Alpha; I already had a RISU test for Arm.
r~
Richard Henderson (4):
fpu: Add float64_to_int{32,64}_modulo
tes
Extract some common code from Alpha and Arm, and which will
shortly also be required by the RISC-V Zfa extension.
Added a new test for Alpha; I already had a RISU test for Arm.
r~
Richard Henderson (4):
fpu: Add float64_to_int{32,64}_modulo
tests/tcg/alpha: Add test for cvttq
target/alpha
