On 12/1/20 2:28 PM, Philippe Mathieu-Daudé wrote:
> Add some MIPS3 and R6 definitions to ease code review.
>
> Philippe Mathieu-Daudé (3):
> target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
> target/mips: Replace CP0_Config0 magic values by proper definitions
> target/mips: Ex
On 12/1/20 7:28 AM, Philippe Mathieu-Daudé wrote:
> Add some MIPS3 and R6 definitions to ease code review.
>
> Philippe Mathieu-Daudé (3):
> target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
> target/mips: Replace CP0_Config0 magic values by proper definitions
> target/mips: Ex
Add some MIPS3 and R6 definitions to ease code review.
Philippe Mathieu-Daudé (3):
target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
target/mips: Replace CP0_Config0 magic values by proper definitions
target/mips: Explicit Release 6 MMU types
target/mips/cpu.h
