On 4/13/21 6:29 PM, Philippe Mathieu-Daudé wrote:> On 4/12/21 4:48 PM,
Peter Maydell wrote:
>> On Mon, 12 Apr 2021 at 15:37, Philippe Mathieu-Daudé wrote:
>>> On 4/12/21 3:43 PM, Peter Maydell wrote:
The AN524 FPGA image supports two memory maps, which differ
in where the QSPI and BRAM a
Hi Peter,
On 4/12/21 4:48 PM, Peter Maydell wrote:
> On Mon, 12 Apr 2021 at 15:37, Philippe Mathieu-Daudé wrote:
>> On 4/12/21 3:43 PM, Peter Maydell wrote:
>>> The AN524 FPGA image supports two memory maps, which differ
>>> in where the QSPI and BRAM are. In the default map, the BRAM
>>> is at 0
On 4/12/21 6:43 AM, Peter Maydell wrote:
Peter Maydell (3):
hw/misc/mps2-scc: Add "QEMU interface" comment
hw/misc/mps2-scc: Support using CFG0 bit 0 for remapping
hw/arm/mps2-tz: Implement AN524 memory remapping via machine property
Reviewed-by: Richard Henderson
r~
On Mon, 12 Apr 2021 at 15:37, Philippe Mathieu-Daudé wrote:
>
> Hi Peter,
>
> On 4/12/21 3:43 PM, Peter Maydell wrote:
> > The AN524 FPGA image supports two memory maps, which differ
> > in where the QSPI and BRAM are. In the default map, the BRAM
> > is at 0x_, and the QSPI at 0x2800_
Hi Peter,
On 4/12/21 3:43 PM, Peter Maydell wrote:
> The AN524 FPGA image supports two memory maps, which differ
> in where the QSPI and BRAM are. In the default map, the BRAM
> is at 0x_, and the QSPI at 0x2800_. In the second
> map, they are the other way around.
>
> In hardware, th
The AN524 FPGA image supports two memory maps, which differ
in where the QSPI and BRAM are. In the default map, the BRAM
is at 0x_, and the QSPI at 0x2800_. In the second
map, they are the other way around.
In hardware, the initial mapping can be selected by the user
by writing either
