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Roan Richmond (1):
Add RISCV ZALASR extension
target/riscv/cpu.c | 1 +
target/riscv/cpu_cfg.h | 1 +
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvzalas
Adds the Atomic Load-Acquire and Store-Release Extension (ZALASR).
This extension is currently frozen, with no changes expected.
The repository for this extension can be found:
https://github.com/riscv/riscv-zalasr.
Roan Richmond (1):
Add RISCV ZALASR extension
target/riscv/cpu.c
