On 10/14/19 3:49 AM, Alex Bennée wrote:
> @@ -190,14 +211,18 @@ static uint64_t * find_counter(struct qemu_plugin_insn
> *insn)
> uint32_t opcode;
> InsnClassExecCount *class = NULL;
>
> -/* we expect all instructions to by 32 bits for ARM */
> -g_assert(qemu_plugin_insn_size(i
On 10/14/19 10:14 AM, Alex Bennée wrote:
>>> -/* we expect all instructions to by 32 bits for ARM */
>>> -g_assert(qemu_plugin_insn_size(insn) == 4);
>>> +/*
>>> + * We only match the first 32 bits of the instruction which is
>>> + * fine for most RISCs but a bit limiting for CI
Richard Henderson writes:
> On 10/14/19 3:49 AM, Alex Bennée wrote:
>> @@ -190,14 +211,18 @@ static uint64_t * find_counter(struct qemu_plugin_insn
>> *insn)
>> uint32_t opcode;
>> InsnClassExecCount *class = NULL;
>>
>> -/* we expect all instructions to by 32 bits for ARM */
>>
Now the plugins interface indicates what guest architecture we are
running we can attempt to select the instruction classification based
on it. For now we still only classify aarch64 instructions and fall
back to decoding individual instructions. We also wave our hands about
irregular instruction e
