On 5/19/22 17:04, Nicholas Piggin wrote:
I'm even more tempted to merge the two files to put all of the machine-specific
cache data
in the same place, then this variable can be static. There's even an existing
TODO
comment in cacheflush.c for aarch64.
That might be nice. Do you want me to lo
Excerpts from Richard Henderson's message of May 20, 2022 4:31 am:
> On 5/19/22 07:11, Nicholas Piggin wrote:
>> dcache writeback and icache invalidate is not required when icache is
>> coherent, a shorter fixed-length sequence can be used which just has to
>> flush and re-fetch instructions that w
On 5/19/22 07:11, Nicholas Piggin wrote:
dcache writeback and icache invalidate is not required when icache is
coherent, a shorter fixed-length sequence can be used which just has to
flush and re-fetch instructions that were in-flight.
Signed-off-by: Nicholas Piggin
---
I haven't been able to
dcache writeback and icache invalidate is not required when icache is
coherent, a shorter fixed-length sequence can be used which just has to
flush and re-fetch instructions that were in-flight.
Signed-off-by: Nicholas Piggin
---
I haven't been able to measure a significant performance differenc
