Re: [PATCH] tcg/riscv: Fix base register for user-only qemu_ld/st

2022-10-25 Thread Alistair Francis
On Mon, Oct 24, 2022 at 1:26 PM Richard Henderson wrote: > > When guest_base != 0, we were not coordinating the usage of > TCG_REG_TMP0 as base properly, leading to a previous zero-extend > of the input address being discarded. > > Shuffle the alignment check to the front, because that does not >

Re: [PATCH] tcg/riscv: Fix base register for user-only qemu_ld/st

2022-10-25 Thread Alistair Francis
On Mon, Oct 24, 2022 at 1:26 PM Richard Henderson wrote: > > When guest_base != 0, we were not coordinating the usage of > TCG_REG_TMP0 as base properly, leading to a previous zero-extend > of the input address being discarded. > > Shuffle the alignment check to the front, because that does not >

Re: [PATCH] tcg/riscv: Fix base register for user-only qemu_ld/st

2022-10-24 Thread LIU Zhiwei
On 2022/10/24 7:33, Richard Henderson wrote: When guest_base != 0, we were not coordinating the usage of TCG_REG_TMP0 as base properly, leading to a previous zero-extend of the input address being discarded. Shuffle the alignment check to the front, because that does not depend on the zero-ext

[PATCH] tcg/riscv: Fix base register for user-only qemu_ld/st

2022-10-23 Thread Richard Henderson
When guest_base != 0, we were not coordinating the usage of TCG_REG_TMP0 as base properly, leading to a previous zero-extend of the input address being discarded. Shuffle the alignment check to the front, because that does not depend on the zero-extend, and it keeps the register usage clear. Set b