On 10/3/21 17:31, Richard Henderson wrote:
> On 10/3/21 10:29 AM, Philippe Mathieu-Daudé wrote:
>> - tcg_gen_shri_i64(t, psw_mask, 16);
>> - tcg_gen_andi_i64(t, t, 0x0f00);
>> + tcg_gen_extract_i64(t, psw_mask, 40, 4);
>
> No, the result should not be at bit 0, but bit 24.
Good catch
On 10/3/21 10:29 AM, Philippe Mathieu-Daudé wrote:
-tcg_gen_shri_i64(t, psw_mask, 16);
-tcg_gen_andi_i64(t, t, 0x0f00);
+tcg_gen_extract_i64(t, psw_mask, 40, 4);
No, the result should not be at bit 0, but bit 24.
r~
When running the scripts/coccinelle/tcg_gen_extract.cocci
Coccinelle semantic patch on target/s390x/, we get:
[DBG] candidate at target/s390x/tcg/translate.c:1560
Manually inspect and replace combinations of (shri, andi)
opcodes by the extract opcode.
Signed-off-by: Philippe Mathieu-Daudé
-
