On Tue, Dec 26, 2023 at 3:29 PM Xu Lu wrote:
>
> The mcycle/minstret counter's stop flag is mistakenly updated on a copy
> on stack. Thus the counter increments even when the CY/IR bit in the
> mcountinhibit register is set. This commit corrects its behavior.
>
> Fixes: 3780e33732f88 (target/riscv
On Tue, Dec 26, 2023 at 3:29 PM Xu Lu wrote:
>
> The mcycle/minstret counter's stop flag is mistakenly updated on a copy
> on stack. Thus the counter increments even when the CY/IR bit in the
> mcountinhibit register is set. This commit corrects its behavior.
>
> Fixes: 3780e33732f88 (target/riscv
26.12.2023 12:21, Daniel Henrique Barboza:
Michael,
This is a good candidate for qemu-trivial. Already acked.
Yeah, I've noticed it it earlier today and already copied to the
qemu-stable-toapply folder :)
Thanks!
/mjt
Michael,
This is a good candidate for qemu-trivial. Already acked.
Thanks,
Daniel
On 12/26/23 01:05, Xu Lu wrote:
The mcycle/minstret counter's stop flag is mistakenly updated on a copy
on stack. Thus the counter increments even when the CY/IR bit in the
mcountinhibit register is set. This c
On 12/26/23 01:05, Xu Lu wrote:
The mcycle/minstret counter's stop flag is mistakenly updated on a copy
on stack. Thus the counter increments even when the CY/IR bit in the
mcountinhibit register is set. This commit corrects its behavior.
Good catch.
Fixes: 3780e33732f88 (target/riscv: Su
The mcycle/minstret counter's stop flag is mistakenly updated on a copy
on stack. Thus the counter increments even when the CY/IR bit in the
mcountinhibit register is set. This commit corrects its behavior.
Fixes: 3780e33732f88 (target/riscv: Support mcycle/minstret write operation)
Signed-off-by:
