Re: [PATCH] target/riscv/cpu.c: fix veyron-v1 CPU properties

2023-06-21 Thread Alistair Francis
On Wed, Jun 21, 2023 at 1:25 AM Daniel Henrique Barboza wrote: > > Commit 7f0bdfb5bfc2 ("target/riscv/cpu.c: remove cfg setup from > riscv_cpu_init()") removed code that was enabling mmu, pmp, ext_ifencei > and ext_icsr from riscv_cpu_init(), the init() function of > TYPE_RISCV_CPU, parent type of

Re: [PATCH] target/riscv/cpu.c: fix veyron-v1 CPU properties

2023-06-20 Thread LIU Zhiwei
On 2023/6/20 23:24, Daniel Henrique Barboza wrote: Commit 7f0bdfb5bfc2 ("target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()") removed code that was enabling mmu, pmp, ext_ifencei and ext_icsr from riscv_cpu_init(), the init() function of TYPE_RISCV_CPU, parent type of all RISC-V CPUss.

Re: [PATCH] target/riscv/cpu.c: fix veyron-v1 CPU properties

2023-06-20 Thread Alistair Francis
On Wed, Jun 21, 2023 at 1:25 AM Daniel Henrique Barboza wrote: > > Commit 7f0bdfb5bfc2 ("target/riscv/cpu.c: remove cfg setup from > riscv_cpu_init()") removed code that was enabling mmu, pmp, ext_ifencei > and ext_icsr from riscv_cpu_init(), the init() function of > TYPE_RISCV_CPU, parent type of

[PATCH] target/riscv/cpu.c: fix veyron-v1 CPU properties

2023-06-20 Thread Daniel Henrique Barboza
Commit 7f0bdfb5bfc2 ("target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()") removed code that was enabling mmu, pmp, ext_ifencei and ext_icsr from riscv_cpu_init(), the init() function of TYPE_RISCV_CPU, parent type of all RISC-V CPUss. This was done to force CPUs to explictly enable all ext