advance.
Shuuichirou.
> -Original Message-
> From: Peter Maydell
> Sent: Wednesday, May 18, 2022 7:31 PM
> To: Ishii, Shuuichirou/石井 周一郎
> Cc: Alex Bennée ; Itaru Kitayama
> ; qemu-...@nongnu.org; qemu-devel@nongnu.org
> Subject: Re: [PATCH] target/arm: Make number of counte
On Wed, 18 May 2022 at 00:24, ishii.shuuic...@fujitsu.com
wrote:
>
> Hi, Peter.
>
> > Shuuichirou, Itaru: this is another patch where we need to know
> > an A64FX register value...
>
> Sorry for the late reply.
>
> The initial value of the pmcr_el0 register in A64FX is 0x46014040.
>
> After applyi
t; Cc: Alex Bennée ; Ishii, Shuuichirou/石井 周一郎
> ; Itaru Kitayama
> Subject: [PATCH] target/arm: Make number of counters in PMCR follow the CPU
>
> Currently we give all the v7-and-up CPUs a PMU with 4 counters. This
> means that we don't provide the 6 counters that are requi
On 5/13/22 05:28, Peter Maydell wrote:
Currently we give all the v7-and-up CPUs a PMU with 4 counters. This
means that we don't provide the 6 counters that are required by the
Arm BSA (Base System Architecture) specification if the CPU supports
the Virtualization extensions.
Instead of having a
Currently we give all the v7-and-up CPUs a PMU with 4 counters. This
means that we don't provide the 6 counters that are required by the
Arm BSA (Base System Architecture) specification if the CPU supports
the Virtualization extensions.
Instead of having a single PMCR_NUM_COUNTERS, make each CPU
On Wed, 31 Mar 2021 at 09:59, Zenghui Yu wrote:
>
> [+kvmarm, Marc]
>
> On 2021/3/12 0:59, Peter Maydell wrote:
> > Currently we give all the v7-and-up CPUs a PMU with 4 counters. This
> > means that we don't provide the 6 counters that are required by the
> > Arm BSA (Base System Architecture) s
[+kvmarm, Marc]
On 2021/3/12 0:59, Peter Maydell wrote:
Currently we give all the v7-and-up CPUs a PMU with 4 counters. This
means that we don't provide the 6 counters that are required by the
Arm BSA (Base System Architecture) specification if the CPU supports
the Virtualization extensions.
I
On 3/11/21 10:59 AM, Peter Maydell wrote:
Currently we give all the v7-and-up CPUs a PMU with 4 counters. This
means that we don't provide the 6 counters that are required by the
Arm BSA (Base System Architecture) specification if the CPU supports
the Virtualization extensions.
Instead of havin
W dniu 11.03.2021 o 17:59, Peter Maydell pisze:
Currently we give all the v7-and-up CPUs a PMU with 4 counters. This
means that we don't provide the 6 counters that are required by the
Arm BSA (Base System Architecture) specification if the CPU supports
the Virtualization extensions.
Instead of
Ping for review, testing, opinions on whether this should go into 6.0 ?
I think I would overall prefer it to the just-bump-PMCR_NUM_COUNTERS
patch...
thanks
-- PMM
On Thu, 11 Mar 2021 at 16:59, Peter Maydell wrote:
>
> Currently we give all the v7-and-up CPUs a PMU with 4 counters. This
> means
Currently we give all the v7-and-up CPUs a PMU with 4 counters. This
means that we don't provide the 6 counters that are required by the
Arm BSA (Base System Architecture) specification if the CPU supports
the Virtualization extensions.
Instead of having a single PMCR_NUM_COUNTERS, make each CPU
11 matches
Mail list logo
