On Sun, Aug 14, 2022 at 3:04 PM Alistair Francis wrote:
>
> On Sat, Aug 13, 2022 at 8:20 PM Peter Maydell
> wrote:
> >
> > On Sat, 13 Aug 2022 at 01:53, Furquan Shaikh wrote:
> > > I ran into a problem when I was testing a project (with a microkernel
> > > in M-mode and tasks in U-mode) that us
On Sat, Aug 13, 2022 at 8:20 PM Peter Maydell wrote:
>
> On Sat, 13 Aug 2022 at 01:53, Furquan Shaikh wrote:
> > I ran into a problem when I was testing a project (with a microkernel
> > in M-mode and tasks in U-mode) that uses semihosting for debugging.
> > The semihosting worked fine for M-mode
On Sat, 13 Aug 2022 at 01:53, Furquan Shaikh wrote:
> I ran into a problem when I was testing a project (with a microkernel
> in M-mode and tasks in U-mode) that uses semihosting for debugging.
> The semihosting worked fine for M-mode but not in U-mode. As I started
> digging into this, I realized
On Fri, Aug 12, 2022 at 7:32 PM Richard Henderson
wrote:
>
> On 8/12/22 17:50, Furquan Shaikh wrote:
> >> Why do you need such fine-grained control? What is the use-case?
> >
> > I ran into a problem when I was testing a project (with a microkernel
> > in M-mode and tasks in U-mode) that uses sem
On 8/12/22 17:50, Furquan Shaikh wrote:
Why do you need such fine-grained control? What is the use-case?
I ran into a problem when I was testing a project (with a microkernel
in M-mode and tasks in U-mode) that uses semihosting for debugging.
The semihosting worked fine for M-mode but not in U
On Fri, Aug 12, 2022 at 5:30 PM Richard Henderson
wrote:
>
> On 8/12/22 16:57, Furquan Shaikh wrote:
> > I am not sure if I understood your comment correctly. Currently, qemu
> > has a check in `riscv_cpu_do_interrupt` to allow semihosting calls
> > only in S and M modes. This prevents semihosting
On 8/12/22 16:57, Furquan Shaikh wrote:
I am not sure if I understood your comment correctly. Currently, qemu
has a check in `riscv_cpu_do_interrupt` to allow semihosting calls
only in S and M modes. This prevents semihosting calls from U mode.
This patch changes the default behavior of checking
On Fri, Aug 12, 2022 at 4:42 PM Richard Henderson
wrote:
>
> On 8/12/22 16:27, Richard Henderson wrote:
> > On 8/11/22 13:41, Furquan Shaikh wrote:
> >> Unlike ARM, RISC-V does not define a separate breakpoint type for
> >> semihosting. Instead, it is entirely ABI. Thus, we need an option
> >> to
On 8/12/22 16:27, Richard Henderson wrote:
On 8/11/22 13:41, Furquan Shaikh wrote:
Unlike ARM, RISC-V does not define a separate breakpoint type for
semihosting. Instead, it is entirely ABI. Thus, we need an option
to allow users to configure what the ebreak behavior should be for
different priv
On Fri, Aug 12, 2022 at 4:00 PM Palmer Dabbelt wrote:
>
> On Fri, 12 Aug 2022 15:05:08 PDT (-0700), furq...@rivosinc.com wrote:
> > On Fri, Aug 12, 2022 at 4:04 AM Andrew Jones
> > wrote:
> >>
> >> On Thu, Aug 11, 2022 at 01:41:04PM -0700, Furquan Shaikh wrote:
> >> > Unlike ARM, RISC-V does not
On 8/11/22 13:41, Furquan Shaikh wrote:
Unlike ARM, RISC-V does not define a separate breakpoint type for
semihosting. Instead, it is entirely ABI. Thus, we need an option
to allow users to configure what the ebreak behavior should be for
different privilege levels - M, S, U, VS, VU. As per the R
On Fri, Aug 12, 2022 at 4:28 AM Peter Maydell wrote:
>
> On Thu, 11 Aug 2022 at 21:47, Furquan Shaikh wrote:
> >
> > Unlike ARM, RISC-V does not define a separate breakpoint type for
> > semihosting. Instead, it is entirely ABI. Thus, we need an option
> > to allow users to configure what the ebr
On Fri, 12 Aug 2022 15:05:08 PDT (-0700), furq...@rivosinc.com wrote:
On Fri, Aug 12, 2022 at 4:04 AM Andrew Jones wrote:
On Thu, Aug 11, 2022 at 01:41:04PM -0700, Furquan Shaikh wrote:
> Unlike ARM, RISC-V does not define a separate breakpoint type for
> semihosting. Instead, it is entirely A
On Fri, Aug 12, 2022 at 4:04 AM Andrew Jones wrote:
>
> On Thu, Aug 11, 2022 at 01:41:04PM -0700, Furquan Shaikh wrote:
> > Unlike ARM, RISC-V does not define a separate breakpoint type for
> > semihosting. Instead, it is entirely ABI. Thus, we need an option
> > to allow users to configure what t
On Thu, 11 Aug 2022 at 21:47, Furquan Shaikh wrote:
>
> Unlike ARM, RISC-V does not define a separate breakpoint type for
> semihosting. Instead, it is entirely ABI. Thus, we need an option
> to allow users to configure what the ebreak behavior should be for
> different privilege levels - M, S, U,
On Thu, Aug 11, 2022 at 01:41:04PM -0700, Furquan Shaikh wrote:
> Unlike ARM, RISC-V does not define a separate breakpoint type for
> semihosting. Instead, it is entirely ABI. Thus, we need an option
> to allow users to configure what the ebreak behavior should be for
> different privilege levels -
On 11/8/22 22:41, Furquan Shaikh wrote:
Unlike ARM, RISC-V does not define a separate breakpoint type for
semihosting. Instead, it is entirely ABI. Thus, we need an option
to allow users to configure what the ebreak behavior should be for
different privilege levels - M, S, U, VS, VU. As per the R
Sorry for the top-posting. I noticed that the patch appears really
weird in patchwork [1] where part of the diff is above the PATCH
section. It looks fine in the archives[2] though.
[1]
https://patchwork.ozlabs.org/project/qemu-devel/patch/ca+tjhd7fcrbtetgro0vzn-xgpmzmqramrw1dw9ia6jzhqni...@mail.
Unlike ARM, RISC-V does not define a separate breakpoint type for
semihosting. Instead, it is entirely ABI. Thus, we need an option
to allow users to configure what the ebreak behavior should be for
different privilege levels - M, S, U, VS, VU. As per the RISC-V
privilege specification[1], ebreak t
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