On Fri, 18 Oct 2024 12:24:05 +0200
Marcin Juszkiewicz wrote:
> W dniu 17.10.2024 o 18:58, Michael S. Tsirkin pisze:
> >> diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
> >> index 4b2f0805c6..54c0f1ec67 100644
> >> --- a/hw/pci/pcie.c
> >> +++ b/hw/pci/pcie.c
> >> @@ -86,7 +86,8 @@ pcie_cap_v1_fill(PC
W dniu 17.10.2024 o 18:58, Michael S. Tsirkin pisze:
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 4b2f0805c6..54c0f1ec67 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -86,7 +86,8 @@ pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type,
uint8_t version)
* Specification, Revi
W dniu 17.10.2024 o 18:58, Michael S. Tsirkin pisze:
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 4b2f0805c6..54c0f1ec67 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -86,7 +86,8 @@ pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type,
uint8_t version)
* Specification, Revi
On Thu, Oct 17, 2024 at 03:33:44PM +0200, Marcin Juszkiewicz wrote:
> PCI has 32 transactions, PCI Express devices can handle 256.
>
> SBSA ACS checks for this capability to be enabled on Arm server systems.
>
> Signed-off-by: Marcin Juszkiewicz
> ---
> SBSA Reference Platform work goes on so I
PCI has 32 transactions, PCI Express devices can handle 256.
SBSA ACS checks for this capability to be enabled on Arm server systems.
Signed-off-by: Marcin Juszkiewicz
---
SBSA Reference Platform work goes on so I am looking at PCIe related tests.
SBSA ACS has test 824 which checks for PCIe dev
