On Fri, 22 Sept 2023 at 19:14, Chris Rauer wrote:
>
> The counter register is only 24-bits and counts down. If the timer is
> running but the qtimer to reset it hasn't fired off yet, there is a chance
> the regster read can return an invalid result.
>
> Signed-off-by: Chris Rauer
Applied to tar
No. This patch does not address that issue and is not related. I was able
to reproduce it about 2/1000 iterations with and without this patch. I
will look into that issue separately.
-Chris
On Fri, Sep 22, 2023 at 11:24 AM Hao Wu wrote:
> Is this related to this error?
>
> https://lists.gnu
Is this related to this error?
https://lists.gnu.org/archive/html/qemu-devel/2023-09/msg04903.html
On Fri, Sep 22, 2023 at 11:14 AM Chris Rauer wrote:
> The counter register is only 24-bits and counts down. If the timer is
> running but the qtimer to reset it hasn't fired off yet, there is a c
The counter register is only 24-bits and counts down. If the timer is
running but the qtimer to reset it hasn't fired off yet, there is a chance
the regster read can return an invalid result.
Signed-off-by: Chris Rauer
---
hw/timer/npcm7xx_timer.c | 3 +++
1 file changed, 3 insertions(+)
diff
