Am 6. Februar 2025 13:49:38 UTC schrieb BALATON Zoltan :
>On Thu, 6 Feb 2025, Philippe Mathieu-Daudé wrote:
>> On 6/2/25 13:49, BALATON Zoltan wrote:
>>> On Thu, 6 Feb 2025, Philippe Mathieu-Daudé wrote:
On 15/1/25 20:04, BALATON Zoltan wrote:
> The interrupt enable registers are not re
On 6/2/25 14:49, BALATON Zoltan wrote:
On Thu, 6 Feb 2025, Philippe Mathieu-Daudé wrote:
On 6/2/25 13:49, BALATON Zoltan wrote:
On Thu, 6 Feb 2025, Philippe Mathieu-Daudé wrote:
On 15/1/25 20:04, BALATON Zoltan wrote:
The interrupt enable registers are not reset to 0 but some bits are
enabled
On Thu, 6 Feb 2025, Philippe Mathieu-Daudé wrote:
On 6/2/25 13:49, BALATON Zoltan wrote:
On Thu, 6 Feb 2025, Philippe Mathieu-Daudé wrote:
On 15/1/25 20:04, BALATON Zoltan wrote:
The interrupt enable registers are not reset to 0 but some bits are
enabled on reset. At least some U-Boot versions
On 6/2/25 13:49, BALATON Zoltan wrote:
On Thu, 6 Feb 2025, Philippe Mathieu-Daudé wrote:
On 15/1/25 20:04, BALATON Zoltan wrote:
The interrupt enable registers are not reset to 0 but some bits are
enabled on reset. At least some U-Boot versions seem to expect this
and not initialise these regis
On Thu, 6 Feb 2025, Philippe Mathieu-Daudé wrote:
On 15/1/25 20:04, BALATON Zoltan wrote:
The interrupt enable registers are not reset to 0 but some bits are
enabled on reset. At least some U-Boot versions seem to expect this
and not initialise these registers before expecting interrupts. The
nu
On 15/1/25 20:04, BALATON Zoltan wrote:
The interrupt enable registers are not reset to 0 but some bits are
enabled on reset. At least some U-Boot versions seem to expect this
and not initialise these registers before expecting interrupts. The
numbers in this patch match what QorIQ P1022 has on r
On Wed, 15 Jan 2025, BALATON Zoltan wrote:
The interrupt enable registers are not reset to 0 but some bits are
enabled on reset. At least some U-Boot versions seem to expect this
and not initialise these registers before expecting interrupts. The
numbers in this patch match what QorIQ P1022 has o
The interrupt enable registers are not reset to 0 but some bits are
enabled on reset. At least some U-Boot versions seem to expect this
and not initialise these registers before expecting interrupts. The
numbers in this patch match what QorIQ P1022 has on reset and fix
U-Boot for this SoC and shoul
