Re: [PATCH] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions

2021-04-19 Thread Frank Chang
On Mon, Apr 19, 2021 at 11:28 PM Richard Henderson < richard.hender...@linaro.org> wrote: > On 4/18/21 10:56 PM, frank.ch...@sifive.com wrote: > > +#elif defined(TARGET_RISCV) > > +/* > > + * For RISC-V, InvalidOp is set when multiplicands are Inf and zero > > + * and returns default N

Re: [PATCH] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions

2021-04-19 Thread Richard Henderson
On 4/18/21 10:56 PM, frank.ch...@sifive.com wrote: +#elif defined(TARGET_RISCV) +/* + * For RISC-V, InvalidOp is set when multiplicands are Inf and zero + * and returns default NaN. + */ +if (infzero) { +float_raise(float_flag_invalid, status); +return 3; +

[PATCH] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions

2021-04-18 Thread frank . chang
From: Frank Chang In IEEE 754-2008 spec: Invalid operation exception is signaled when doing: fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c) unless c is a quiet NaN; if c is a quiet NaN then it is implementation defined whether the invalid operation exception is signaled. In