Re: [PATCH] RISC-V: Allow both Zmmul and M

2022-07-17 Thread Alistair Francis
On Fri, Jul 15, 2022 at 4:13 AM Palmer Dabbelt wrote: > > We got to talking about how Zmmul and M interact with each other > https://github.com/riscv/riscv-isa-manual/issues/869 , and it turns out > that QEMU's behavior is slightly wrong: having Zmmul and M is a legal > combination, it just means

Re: [PATCH] RISC-V: Allow both Zmmul and M

2022-07-17 Thread Alistair Francis
On Fri, Jul 15, 2022 at 4:13 AM Palmer Dabbelt wrote: > > We got to talking about how Zmmul and M interact with each other > https://github.com/riscv/riscv-isa-manual/issues/869 , and it turns out > that QEMU's behavior is slightly wrong: having Zmmul and M is a legal > combination, it just means

[PATCH] RISC-V: Allow both Zmmul and M

2022-07-14 Thread Palmer Dabbelt
We got to talking about how Zmmul and M interact with each other https://github.com/riscv/riscv-isa-manual/issues/869 , and it turns out that QEMU's behavior is slightly wrong: having Zmmul and M is a legal combination, it just means that the multiplication instructions are supported even when M is