Hello Francis,
Yes thank you. I added code to setup a basic PMP and it works now. Thank
you and best regards,
Teodori Serge
On Sun, 18 Apr 2021, 05:55 Alistair Francis, <1923...@bugs.launchpad.net>
wrote:
> We fixed a bug to make QEMU act more like hardware, which now means that
> PMP must be c
We fixed a bug to make QEMU act more like hardware, which now means that
PMP must be configured in M-mode.
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https://bugs.launchpad.net/bugs/1923197
Title:
RISC-V priviledged instructio
Hello Francis,
I'll configure PMP than do the test again. Sorry I hadn't understood what
changed between version 5.2 and 6.0-rc2, since my code worked before.
Best regards,
Teodori Serge
On Thu, 15 Apr 2021, 06:15 Alistair Francis, <1923...@bugs.launchpad.net>
wrote:
> I'm guessing that this is
I'm guessing that this is a bug in your guest as it hasn't configured
PMP regions.
>From the RISC-V spec:
"
If no PMP entry matches an M-mode access, the access succeeds. If no PMP entry
matches an
S-mode or U-mode access, but at least one PMP entry is implemented, the access
fails.
"
Confusin
You can check this by reverting this QEMU commit:
commit d102f19a2085ac931cb998e6153b73248cca49f1
Author: Atish Patra
Date: Wed Dec 23 11:25:53 2020 -0800
target/riscv/pmp: Raise exception if no PMP entry is configured
As per the privilege specification, any access from S/U mode s
** Changed in: qemu
Status: New => Confirmed
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You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1923197
Title:
RISC-V priviledged instruction error
Status in QEMU:
Confirmed
Bug description:
