This is an automated cleanup. This bug report has been moved
to QEMU's new bug tracker on gitlab.com and thus gets marked
as 'expired' now. Please continue with the discussion here:
https://gitlab.com/qemu-project/qemu/-/issues/53
** Changed in: qemu
Status: New => Expired
** Bug watch
** Changed in: qemu
Status: Incomplete => New
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https://bugs.launchpad.net/bugs/1826568
Title:
RISC-V Disassembler/translator instruction decoding disagreement
Status in QEMU:
The QEMU project is currently considering to move its bug tracking to another
system. For this we need to know which bugs are still valid and which could be
closed already. Thus we are setting older bugs to "Incomplete" now.
If you still think this bug report here is valid, then please switch the
I've encountered this message before for invalid instructions, and it
often doesn't really mean there was an error. In particular for variable
instruction length ISAs you'll see the error if the translator reads
part of the insn and determines that it's invalid without needing to
read the rest of i
Sorry, I don't have the test code, since this was created by a memory
corruption. However, the way I understand the message is, that there is
some internal disagreement how to decode the op-code "05139517e2bf"
- which mige be an invalid opcode anyway. So a simple test application
would just con
Hi Axel,
can you link us to your test code, such that we can try to reproduce it.
Cheers,
Bastian
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https://bugs.launchpad.net/bugs/1826568
Title:
RISC-V Disassembler/translator instr
