[PATCH v2 3/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_SMSTATEEN

Add KVM_REG_RISCV_CSR_SMSTATEEN support to get/set the context of Smstateen extension in VS mode. Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c

[PATCH v2 5/8] target/riscv/kvm: rewrite kvm_riscv_handle_csr

related VS mode context of the CSR can be loaded from host in context_load() hook. After the CSR handling, the modified VS context is written back in context_put() hook. Signed-off-by: Yong-Xuan Wang --- target/riscv/cpu.h | 2 -- target/riscv/csr.c | 18 +++--- target/riscv

[PATCH v2 4/8] target/riscv: add helper to get CSR name

Add a helper function to get CSR name from CSR number. Signed-off-by: Yong-Xuan Wang --- target/riscv/cpu.h | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 616c3bdc1c24..df10ff63474b 100644 --- a/target/riscv/cpu.h +++ b

[PATCH v2 2/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_AIA

Add KVM_REG_RISCV_CSR_AIA support to get/set the context of AIA extension in VS mode. Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 45 ++ 1 file changed, 45 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c

[PATCH v2 8/8] hw/intc/imsic: prevent to use IMSIC when host doesn't support AIA extension

uses the IMSIC devices when the host kernel supports the AIA extension. Signed-off-by: Yong-Xuan Wang --- hw/intc/riscv_imsic.c | 17 + 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index dc8162c0a7c9..8c64f2c21274 1

[PATCH v2 1/8] target/riscv/kvm: rewrite get/set for KVM_REG_RISCV_CSR

As KVM_REG_RISCV_CSR includes several subtypes of CSR, rewrite the related macros and functions to prepare for other subtypes. Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 70 +++--- 1 file changed, 43 insertions(+), 27 deletions(-) diff --git

[PATCH v2 6/8] target/riscv/kvm: add CSR_SIREG and CSR_STOPEI emulation

machine lacks M-mode CSRs and does not report S-mode support in its environment configuration, even though some S-mode CSRs are accessible. This patch adds kvm_enabled() checks in relevant predicates to ensure proper handling and validation. Signed-off-by: Yong-Xuan Wang --- target/riscv/csr.c

[PATCH v2 7/8] docs: update the description about RISC-V AIA

Add the description about "-accel kvm,kernel-irqchip=off" into docs/specs/riscv-aia.rst and docs/system/riscv/virt.rst. Signed-off-by: Yong-Xuan Wang --- docs/specs/riscv-aia.rst | 24 ++-- docs/system/riscv/virt.rst | 10 ++ 2 files changed, 24 inserti

[PATCH v2 0/8] riscv: AIA: kernel-irqchip=off support

PATCH8 to prevent the usage of IMSIC devices when the host machine doesn't support the AIA extension. - fix typo in cover letter Yong-Xuan Wang (8): target/riscv/kvm: rewrite get/set for KVM_REG_RISCV_CSR target/riscv/kvm: add KVM_REG_RISCV_CSR_AIA target/riscv/kvm: add KVM_REG_RISCV_C

Re: [PATCH 4/8] target/riscv: add helper to get CSR name

Hi Andrew, On Mon, Feb 17, 2025 at 10:01 PM Andrew Jones wrote: > > On Mon, Feb 17, 2025 at 04:17:24PM +0800, Yong-Xuan Wang wrote: > > Add a helper function to get CSR name from CSR number. > > > > Signed-off-by: Yong-Xuan Wang > > --- > > target/riscv/cpu

Re: [PATCH 0/8] riscv: AIA: kernel-irqchip=off support

Hi Kashyap, On Tue, Feb 18, 2025 at 11:53 PM Kashyap Chamarthy wrote: > > On Mon, Feb 17, 2025 at 04:17:20PM +0800, Yong-Xuan Wang wrote: > > This series introduces the user-space AIA MSI emulation when using KVM > > acceleration. > > > > After this series, RIS

[PATCH v2 2/3] hw/intc/aplic: refine the APLIC realize

before checking failed. Signed-off-by: Yong-Xuan Wang --- hw/intc/riscv_aplic.c | 49 +++ 1 file changed, 26 insertions(+), 23 deletions(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 0974c6a5db39..e5714267c096 100644 --- a/hw/intc

[PATCH v2 3/3] hw/intc/aplic: refine kvm_msicfgaddr

Let kvm_msicfgaddr use the same format with mmsicfgaddr and smsicfgaddr. Signed-off-by: Yong-Xuan Wang --- hw/intc/riscv_aplic.c | 24 +--- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index e5714267c096

[PATCH v2 1/3] hw/intc/imsic: refine the IMSIC realize

IMSIC realization. This can avoid the unnecessary resource allocation before checking failed. Signed-off-by: Yong-Xuan Wang --- hw/intc/riscv_imsic.c | 47 --- 1 file changed, 26 insertions(+), 21 deletions(-) diff --git a/hw/intc/riscv_imsic.c b/hw/intc

[PATCH v2 0/3] riscv: AIA: refinement for KVM acceleration

Reorder the code to reduce the conditional checking and remove unnecessary resource setting when using in-kernl AIA irqchip. --- v2: - remove the code reordering of the riscv-virt machine since it can't work with NUMA setting. (Daniel) Yong-Xuan Wang (3): hw/intc/imsic: refine the

Re: [PATCH 7/8] target/riscv/kvm: rename riscv-aia to riscv-imsic

Hi Andrew, On Mon, Feb 17, 2025 at 10:07 PM Andrew Jones wrote: > > On Mon, Feb 17, 2025 at 04:17:27PM +0800, Yong-Xuan Wang wrote: > > The riscv-aia property only controls the in-kernel IMSIC mode, the > > emulation of AIA MSI mode is controlled by the kernel-irqchip proper

Re: [PATCH 1/4] hw/riscv/virt: KVM AIA refinement

Hi Daniel, On Tue, Feb 18, 2025 at 3:24 AM Daniel Henrique Barboza wrote: > > > > On 2/17/25 5:19 AM, Yong-Xuan Wang wrote: > > KVM AIA is only needed to be set when the virt machine use the AIA MSI. > > So we can move the KVM AIA configuration into virt_create_aia() to

[PATCH 7/8] target/riscv/kvm: rename riscv-aia to riscv-imsic

The riscv-aia property only controls the in-kernel IMSIC mode, the emulation of AIA MSI mode is controlled by the kernel-irqchip property. Rename the riscv-aia property to riscv-imsic to prevent the confusion. Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 52

[PATCH 2/4] hw/intc/imsic: refine the IMSIC realize

IMSIC realization. This can avoid the unnecessary resource allocation before checking failed. Signed-off-by: Yong-Xuan Wang --- hw/intc/riscv_imsic.c | 47 --- 1 file changed, 26 insertions(+), 21 deletions(-) diff --git a/hw/intc/riscv_imsic.c b/hw/intc

[PATCH 0/4] riscv: AIA: refinement for KVM acceleration

Reorder the code to reduce the conditional checking and remove unnecessary resource setting when using in-kernl AIA irqchip. Yong-Xuan Wang (4): hw/riscv/virt: KVM AIA refinement hw/intc/imsic: refine the IMSIC realize hw/intc/aplic: refine the APLIC realize hw/intc/aplic: refine

[PATCH 3/4] hw/intc/aplic: refine the APLIC realize

before checking failed. Signed-off-by: Yong-Xuan Wang --- hw/intc/riscv_aplic.c | 49 +++ 1 file changed, 26 insertions(+), 23 deletions(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 0974c6a5db39..e5714267c096 100644 --- a/hw/intc

[PATCH 4/4] hw/intc/aplic: refine kvm_msicfgaddr

Let kvm_msicfgaddr use the same format with mmsicfgaddr and smsicfgaddr. Signed-off-by: Yong-Xuan Wang --- hw/intc/riscv_aplic.c | 24 +--- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index e5714267c096

[PATCH 2/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_AIA

Add KVM_REG_RISCV_CSR_AIA support to get/set the context of AIA extension in VS mode. Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 45 ++ 1 file changed, 45 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c

[PATCH 4/8] target/riscv: add helper to get CSR name

Add a helper function to get CSR name from CSR number. Signed-off-by: Yong-Xuan Wang --- target/riscv/cpu.h | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 616c3bdc1c24..133d1852ee1e 100644 --- a/target/riscv/cpu.h +++ b

[PATCH 1/4] hw/riscv/virt: KVM AIA refinement

KVM AIA is only needed to be set when the virt machine use the AIA MSI. So we can move the KVM AIA configuration into virt_create_aia() to reduce the condition checking. Signed-off-by: Yong-Xuan Wang --- hw/riscv/virt.c | 79 +++-- 1 file changed, 37

[PATCH 5/8] target/riscv/kvm: rewrite kvm_riscv_handle_csr

related VS mode context of the CSR can be loaded from host in context_load() hook. After the CSR handling, the modified VS context is written back in context_put() hook. Signed-off-by: Yong-Xuan Wang --- target/riscv/cpu.h | 2 -- target/riscv/csr.c | 18 +++--- target/riscv

[PATCH 3/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_SMSTATEEN

Add KVM_REG_RISCV_CSR_SMSTATEEN support to get/set the context of Smstateen extension in VS mode. Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c

[PATCH 8/8] docs: update the description about RISC-V AIA

Add the description about "-accel kvm,kernel-irqchip=off" into docs/specs/riscv-aia.rst and docs/system/riscv/virt.rst. Signed-off-by: Yong-Xuan Wang --- docs/specs/riscv-aia.rst | 24 ++-- docs/system/riscv/virt.rst | 10 ++ 2 files changed, 24 inserti

[PATCH 0/8] riscv: AIA: kernel-irqchip=off support

hardware guest IMSICs whenever available otherwise fallback to MRIF Yong-Xuan Wang (8): target/riscv/kvm: rewrite get/set for KVM_REG_RISCV_CSR target/riscv/kvm: add KVM_REG_RISCV_CSR_AIA target/riscv/kvm: add KVM_REG_RISCV_CSR_SMSTATEEN target/riscv: add helper to get CSR name target/risc

[PATCH 1/8] target/riscv/kvm: rewrite get/set for KVM_REG_RISCV_CSR

As KVM_REG_RISCV_CSR includes several subtypes of CSR, rewrite the related macros and functions to prepare for other subtypes. Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 70 +++--- 1 file changed, 43 insertions(+), 27 deletions(-) diff --git

[PATCH 6/8] target/riscv/kvm: add CSR_SIREG and CSR_STOPEI emulation

machine lacks M-mode CSRs and does not report S-mode support in its environment configuration, even though some S-mode CSRs are accessible. This patch adds kvm_enabled() checks in relevant predicates to ensure proper handling and validation. Signed-off-by: Yong-Xuan Wang --- target/riscv/csr.c

Re: [PATCH 1/1] hw/riscv: virt: prevent to use AIA MSI when host doesn't support it

opei CSR in KVM We need to update the kvm_riscv_handle_csr() for situation 2. And it's better to determine the availability of AIA extension in riscv_imsic_realize(). Please ignore this patch, I will send another patchset to handle the above situations. Regards, Yong-Xuan On Mon, Nov 4,

Re: [PATCH 1/1] hw/riscv: virt: prevent to use AIA MSI when host doesn't support it

VM AIA(MSI) without in-kernel AIA irqchip support. Regards, Yong-Xuan On Fri, Nov 1, 2024 at 11:09 PM Andrew Jones wrote: > > On Fri, Nov 01, 2024 at 08:45:13AM -0300, Daniel Henrique Barboza wrote: > > > > > > On 11/1/24 5:36 AM, Yong-Xuan Wang wrote: > > > Curr

[PATCH 1/1] hw/riscv: virt: prevent to use AIA MSI when host doesn't support it

guest OS only uses the AIA MSI device when the host kernel supports the in-kernel AIA chip. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- hw/riscv/virt.c | 19 +-- 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c

[PATCH v2 1/1] hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation

ut value is low, when the interrupt is forwarded by MSI, or by a relevant write to an in_clrip register or to clripnum." Update the riscv_aplic_set_pending() to match the spec. Fixes: bf31cf06eb ("hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode") Signed-

Re: [PATCH 1/1] hw/intc/riscv_aplic: Fix APLIC in clrip and clripnum write emulation

ping On Fri, Aug 9, 2024 at 11:28 AM Yong-Xuan Wang wrote: > > Hi Daniel, > > On Fri, Aug 9, 2024 at 5:40 AM Daniel Henrique Barboza > wrote: > > > > Ccing Anup > > > > On 8/8/24 5:20 AM, Yong-Xuan Wang wrote: > > > In the section "4.7 Pr

[PATCH v2 1/1] hw/intc/riscv_aplic: Check and update pending when write sourcecfg

ding status for us when writing sourcecfg registers. Update QEMU emulation to handle "pre-existing" interrupts. Signed-off-by: Yong-Xuan Wang Acked-by: Alistair Francis --- v2: - fix checkpatch warning --- hw/intc/riscv_aplic.c | 51 --- 1 fi

Re: [PATCH 1/1] hw/intc/riscv_aplic: Check and update pending when write sourcecfg

Hi Alistair, On Mon, Sep 9, 2024 at 10:32 AM Alistair Francis wrote: > > On Thu, Aug 8, 2024 at 6:21 PM Yong-Xuan Wang > wrote: > > > > The section 4.5.2 of the RISC-V AIA specification says that any write > > to a sourcecfg register of an APLIC might (or might not)

Re: [PATCH 1/1] hw/intc/riscv_aplic: Fix APLIC in clrip and clripnum write emulation

Hi Daniel, On Fri, Aug 9, 2024 at 5:40 AM Daniel Henrique Barboza wrote: > > Ccing Anup > > On 8/8/24 5:20 AM, Yong-Xuan Wang wrote: > > In the section "4.7 Precise effects on interrupt-pending bits" > > of the RISC-V AIA specification defines that: > > &g

[PATCH 1/1] hw/intc/riscv_aplic: Fix APLIC in clrip and clripnum write emulation

lue is low, when the interrupt is forwarded by MSI, or by a relevant write to an in clrip register or to clripnum. Update the riscv_aplic_set_pending() to match the spec. Signed-off-by: Yong-Xuan Wang --- hw/intc/riscv_aplic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH 1/1] hw/intc/riscv_aplic: Check and update pending when write sourcecfg

ding status for us when writing sourcecfg registers. Update QEMU emulation to handle "pre-existing" interrupts. Signed-off-by: Yong-Xuan Wang --- hw/intc/riscv_aplic.c | 49 +++ 1 file changed, 31 insertions(+), 18 deletions(-) diff --git a/h

[PATCH v2 1/1] target/riscv/kvm.c: Fix the hart bit setting of AIA

accurate hart-index-bit settings. Additionally, a Linux patch[1] is necessary to correctly recover the hart index when the guest OS has only 1 hart, where the hart-index-bit is 0. [1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.w...@sifive.com/t/ Signed-off-by: Yong-Xuan Wang

Re: [PATCH 1/1] target/riscv/kvm.c: Fix the hart bit setting of AIA

Hi Alistair, On Mon, Apr 29, 2024 at 11:25 AM Alistair Francis wrote: > > On Mon, Apr 15, 2024 at 4:53 PM Yong-Xuan Wang > wrote: > > > > The hart bit setting is different with Linux AIA driver[1] when the number > > of hart is power of 2. For example, when

[PATCH 1/1] target/riscv/kvm.c: Fix the hart bit setting of AIA

accurate result. [1] https://lore.kernel.org/all/20240307140307.646078-1-apa...@ventanamicro.com/ Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index

Re: [PATCH net v4] virtio_net: Do not send RSS key if it is not supported

realizes that the > vitio is broken at QEMU side. > > Fix it by not sending RSS commands if the feature is not available in > the device. > > Fixes: c7114b1249fa ("drivers/net/virtio_net: Added basic RSS support.") > Cc: sta...@vger.kernel.org > Cc: qemu-devel@nongnu.org

Re: [PATCH] virtio_net: Do not send RSS key if it is not supported

On Mon, 25 Mar 2024 04:26:08 -0700, Breno Leitao wrote: > Hello Xuan, > > On Mon, Mar 25, 2024 at 01:57:53PM +0800, Xuan Zhuo wrote: > > On Fri, 22 Mar 2024 03:21:21 -0700, Breno Leitao wrote: > > > Hello Xuan, > > > > > > On Fri, Mar 22, 2024 at 10:00:2

Re: [PATCH] virtio_net: Do not send RSS key if it is not supported

On Fri, 22 Mar 2024 03:21:21 -0700, Breno Leitao wrote: > Hello Xuan, > > On Fri, Mar 22, 2024 at 10:00:22AM +0800, Xuan Zhuo wrote: > > On Thu, 21 Mar 2024 09:54:30 -0700, Breno Leitao wrote: > > > > 4) Since the command above does not have a key, then the last &g

Re: qemu fuzz crash in virtio_net_queue_reset()

On Wed, 20 Mar 2024 00:24:37 +0300, "Vladimir Sementsov-Ogievskiy" wrote: > Hi all! > > From fuzzing I've got a fuzz-data, which produces the following crash: > > qemu-fuzz-x86_64: ../hw/net/virtio-net.c:134: void > flush_or_purge_queued_packets(NetClientState *): Assertion > `!virtio_net_get_

Re: [PATCH] virtio_net: Do not send RSS key if it is not supported

On Thu, 21 Mar 2024 09:54:30 -0700, Breno Leitao wrote: > There is a bug when setting the RSS options in virtio_net that can break > the whole machine, getting the kernel into an infinite loop. > > Running the following command in any QEMU virtual machine with virtionet > will reproduce this probl

[PATCH v2 1/1] target/riscv/kvm: fix timebase-frequency when using KVM acceleration

The timebase-frequency of guest OS should be the same with host machine. The timebase-frequency value in DTS should be got from hypervisor when using KVM acceleration. Reviewed-by: Andrew Jones Signed-off-by: Yong-Xuan Wang --- Changelog v2: - update the function definition - restructure if

[PATCH 1/1] target/riscv/kvm: fix timebase-frequency when using KVM acceleration

The timebase-frequency of guest OS should be the same with host machine. The timebase-frequency value in DTS should be got from hypervisor when using KVM acceleration. Signed-off-by: Yong-Xuan Wang --- hw/riscv/virt.c | 11 +-- target/riscv/kvm/kvm-cpu.c | 9

[PATCH 1/1] target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket

y one socket, as its address space might not contain the group shift. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- target/riscv/kvm/kvm-cpu.c | 31 +-- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kv

[PATCH 1/1] hw/riscv/virt.c: fix the interrupts-extended property format of PLIC

-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- hw/riscv/virt.c | 47 +++ 1 file changed, 27 insertions(+), 20 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d2eac2415619..e42baf82cab6 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv

[PATCH v7 2/5] target/riscv: check the in-kernel irqchip support

We check the in-kernel irqchip support when using KVM acceleration. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target

[PATCH v7 0/5] Add RISC-V KVM AIA Support

sepecify the KVM AIA mode in PATCH6 v3: - fix typo - tag the linux-header patch as placeholder v2: - rebase to riscv-to-apply.next - update the linux header by the scripts/update-linux-headers.sh Yong-Xuan Wang (5): target/riscv: support the AIA device emulation with KVM enabled target/ri

[PATCH v7 3/5] target/riscv: Create an KVM AIA irqchip

;: IMSIC is emulated by hypervisor 2) "riscv-aia=hwaccel": use hardware guest IMSIC 3) "riscv-aia=auto": use the hardware guest IMSICs whenever available otherwise we fallback to software emulation. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Review

[PATCH v7 4/5] target/riscv: update APLIC and IMSIC to support KVM AIA

messages are delivered by KVM_SIGNAL_MSI API when the IMSICs receive mmio write requests. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- hw/intc/riscv_aplic.c | 56 ++- h

[PATCH v7 1/5] target/riscv: support the AIA device emulation with KVM enabled

In this patch, we create the APLIC and IMSIC FDT helper functions and remove M mode AIA devices when using KVM acceleration. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- hw/riscv/virt.c | 290

[PATCH v7 5/5] target/riscv: select KVM AIA in riscv virt machine

Select KVM AIA when the host kernel has in-kernel AIA chip support. Since KVM AIA only has one APLIC instance, we map the QEMU APLIC devices to KVM APLIC. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- hw/riscv/virt.c

[PATCH v6 4/5] target/riscv: update APLIC and IMSIC to support KVM AIA

messages are delivered by KVM_SIGNAL_MSI API when the IMSICs receive mmio write requests. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- hw/intc/riscv_aplic.c | 56 ++- h

[PATCH v6 1/5] target/riscv: support the AIA device emulation with KVM enabled

In this patch, we create the APLIC and IMSIC FDT helper functions and remove M mode AIA devices when using KVM acceleration. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- hw/riscv/virt.c | 290

[PATCH v6 5/5] target/riscv: select KVM AIA in riscv virt machine

nd-line. 1) "kvm-aia=emul": IMSIC is emulated by hypervisor 2) "kvm-aia=hwaccel": use hardware guest IMSIC 3) "kvm-aia=auto": use the hardware guest IMSICs whenever available otherwise we fallback to software emulation. Signed-off-by: Yong-Xuan Wang R

[PATCH v6 2/5] target/riscv: check the in-kernel irqchip support

We check the in-kernel irqchip support when using KVM acceleration. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target

[PATCH v6 3/5] target/riscv: Create an KVM AIA irqchip

We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm.c | 160

[PATCH v6 0/5] Add RISC-V KVM AIA Support

IA devices mapping with NUMA enabled in PATCH6 - add "kvm-aia" parameter to sepecify the KVM AIA mode in PATCH6 v3: - fix typo - tag the linux-header patch as placeholder v2: - rebase to riscv-to-apply.next - update the linux header by the scripts/update-linux-headers.sh Yong-Xuan Wang

[PATCH v5 3/5] target/riscv: Create an KVM AIA irqchip

We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza --- target/riscv/kvm.c | 160 +++ target

[PATCH v5 1/5] target/riscv: support the AIA device emulation with KVM enabled

In this patch, we create the APLIC and IMSIC FDT helper functions and remove M mode AIA devices when using KVM acceleration. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 264 ++-- 1

[PATCH v5 4/5] target/riscv: update APLIC and IMSIC to support KVM AIA

messages are delivered by KVM_SIGNAL_MSI API when the IMSICs receive mmio write requests. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- hw/intc/riscv_aplic.c | 56 ++- h

[PATCH v5 2/5] target/riscv: check the in-kernel irqchip support

We check the in-kernel irqchip support when using KVM acceleration. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza --- target/riscv/kvm.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv

[PATCH v5 0/5] Add RISC-V KVM AIA Support

the KVM AIA mode in PATCH6 v3: - fix typo - tag the linux-header patch as placeholder v2: - rebase to riscv-to-apply.next - update the linux header by the scripts/update-linux-headers.sh Yong-Xuan Wang (5): target/riscv: support the AIA device emulation with KVM enabled target/riscv: check t

[PATCH v5 5/5] target/riscv: select KVM AIA in riscv virt machine

nd-line. 1) "kvm-aia=emul": IMSIC is emulated by hypervisor 2) "kvm-aia=hwaccel": use hardware guest IMSIC 3) "kvm-aia=auto": use the hardware guest IMSICs whenever available otherwise we fallback to software emulation. Signed-off-by: Yong-Xuan Wang R

Re: [PATCH v4 0/6] Add RISC-V KVM AIA Support

Hi Andrew, I'll add it into patch v5. Thank you! Regards, Yong-Xuan On Wed, Jul 5, 2023 at 4:14 PM Andrew Jones wrote: > > On Wed, Jun 21, 2023 at 02:54:50PM +, Yong-Xuan Wang wrote: > > This series adds support for KVM AIA in RISC-V architecture. > > > > In or

[PATCH v4 4/6] target/riscv: Create an KVM AIA irqchip

implement a function to create an KVM AIA chip Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- target/riscv/kvm.c | 163 +++ target/riscv/kvm_riscv.h | 6 ++ 2 files changed, 169 insertions(+) diff --git a/target/riscv/kvm.c b/target/riscv

[PATCH v4 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support placeholder

/20230404153452.2405681-1-apa...@ventanamicro.com/ [2] https://www.spinics.net/lists/kernel/msg4791872.html Currently, patchset 1 is already merged into mainline kernel in v6.4-rc1 and patchset 2 is not. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- linux-headers/asm-riscv/kvm.h | 123

[PATCH v4 5/6] target/riscv: update APLIC and IMSIC to support KVM AIA

messages are delivered by KVM_SIGNAL_MSI API when the IMSICs receive mmio write requests. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- hw/intc/riscv_aplic.c | 58 +++ hw/intc/riscv_imsic.c | 26 +++ 2 files changed, 63 insertions(+), 21

[PATCH v4 6/6] target/riscv: select KVM AIA in riscv virt machine

nd-line. 1) "kvm-aia=emul": IMSIC is emulated by hypervisor 2) "kvm-aia=hwaccel": use hardware guest IMSIC 3) "kvm-aia=auto": use the hardware guest IMSICs whenever available otherwise we fallback to software emulation. Signed-off-by: Yong-Xuan Wang Re

[PATCH v4 2/6] target/riscv: support the AIA device emulation with KVM enabled

Remove M mode AIA devices when using KVM acceleration Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- hw/riscv/virt.c | 207 +--- 1 file changed, 108 insertions(+), 99 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index

[PATCH v4 3/6] target/riscv: check the in-kernel irqchip support

We check the in-kernel irqchip support when using KVM acceleration. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza --- target/riscv/kvm.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target

[PATCH v4 0/6] Add RISC-V KVM AIA Support

TCH6 - add "kvm-aia" parameter to sepecify the KVM AIA mode in PATCH6 v3: - fix typo - tag the linux-header patch as placeholder v2: - rebase to riscv-to-apply.next - update the linux header by the scripts/update-linux-headers.sh Yong-Xuan Wang (6): update-linux-headers: sync-up header wi

Re: [PATCH v3 2/6] target/riscv: support the AIA device emulation with KVM enabled

Hi Daniel, I think this checking can be removed too. Would you send a patch to fix it? Or I can remove it in this patch. Regards, Yong-Xuan On Tue, Jun 6, 2023 at 2:45 AM Daniel Henrique Barboza wrote: > > > > On 5/26/23 03:25, Yong-Xuan Wang wrote: > > Remove M mode AIA devi

Re: [PATCH v3 4/6] target/riscv: Create an KVM AIA irqchip

Hi Daniel, Thanks for your suggestions! I'll fix it in patch v4. Regards, Yong-Xuan On Tue, Jun 6, 2023 at 9:45 PM Daniel Henrique Barboza wrote: > > > > On 5/26/23 03:25, Yong-Xuan Wang wrote: > > implement a function to create an KVM AIA chip > > >

[PATCH v3 4/6] target/riscv: Create an KVM AIA irqchip

implement a function to create an KVM AIA chip Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- target/riscv/kvm.c | 83 target/riscv/kvm_riscv.h | 3 ++ 2 files changed, 86 insertions(+) diff --git a/target/riscv/kvm.c b/target/riscv

[PATCH v3 2/6] target/riscv: support the AIA device emulation with KVM enabled

Remove M mode AIA devices when using KVM acceleration Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- hw/riscv/virt.c | 199 +--- 1 file changed, 105 insertions(+), 94 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index

[PATCH v3 3/6] target/riscv: check the in-kernel irqchip support

We check the in-kernel irqchip support when using KVM acceleration. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- target/riscv/kvm.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 0f932a5b96..eb469e8ca5

[PATCH v3 5/6] target/riscv: update APLIC and IMSIC to support KVM AIA

- Do not set the mmio operations of APLIC and IMSIC when using KVM AIA - Send interrupt signal to KVM AIA via KVM_IRQ_LINE API Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- hw/intc/riscv_aplic.c | 19 +++ hw/intc/riscv_imsic.c | 16 +++- 2 files changed, 26

[PATCH v3 0/6] Add RISC-V KVM AIA Support

This series adds support for KVM AIA in RISC-V architecture. In order to test these patches, we require Linux with KVM AIA support which can be found in the qemu_kvm_aia branch at https://github.com/yong-xuan/linux.git This kernel branch is based on the riscv_aia_v1 branch available at https

[PATCH v3 6/6] target/riscv: select KVM AIA in riscv virt machine

Select KVM AIA when the host kernel has in-kernel AIA chip support. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- hw/riscv/virt.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 18b94888ab..57a07fa6c5 100644 --- a/hw/riscv/virt.c

[PATCH v3 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support placeholder

/20230404153452.2405681-1-apa...@ventanamicro.com/ [2] https://www.spinics.net/lists/kernel/msg4791872.html Currently, patchset 1 is already merged into mainline kernel in v6.4-rc1 and patchset 2 is not. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- linux-headers/linux/kvm.h | 2 ++ target/riscv

Re: [PTACH v2 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support

On Mon, May 8, 2023 at 3:39 PM Cornelia Huck wrote: > > On Fri, May 05 2023, Alex Williamson wrote: > > > On Fri, 5 May 2023 11:39:36 +0000 > > Yong-Xuan Wang wrote: > > > >> Update the linux headers to get the latest KVM RISC-V headers with AIA > >

Re: [PATCH] virtio-net: not enable vq reset feature unconditionally

On Mon, 8 May 2023 11:09:46 +0200, Eugenio Perez Martin wrote: > On Sat, May 6, 2023 at 4:25 AM Xuan Zhuo wrote: > > > > On Thu, 4 May 2023 12:14:47 +0200, =?utf-8?q?Eugenio_P=C3=A9rez?= > > wrote: > > > The commit 93a97dc5200a ("virtio-net

Re: [PATCH] virtio-net: not enable vq reset feature unconditionally

On Mon, 8 May 2023 14:44:21 +0800, Jason Wang wrote: > On Sun, May 7, 2023 at 2:01 PM Michael S. Tsirkin wrote: > > > > On Sat, May 06, 2023 at 10:13:36AM +0800, Xuan Zhuo wrote: > > > On Thu, 4 May 2023 12:14:47 +0200, =?utf-8?q?Eugenio_P=C3=A9rez?= > >

Re: [PATCH] virtio-net: not enable vq reset feature unconditionally

On Thu, 4 May 2023 12:14:47 +0200, =?utf-8?q?Eugenio_P=C3=A9rez?= wrote: > The commit 93a97dc5200a ("virtio-net: enable vq reset feature") enables > unconditionally vq reset feature as long as the device is emulated. > This makes impossible to actually disable the feature, and it causes > migrat

[PTACH v2 6/6] target/riscv: select KVM AIA in riscv virt machine

Select KVM AIA when the host kernel has in-kernel AIA chip support. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- hw/riscv/virt.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 396025b5a5..9fad01a5ab 100644 --- a/hw/riscv/virt.c

[PTACH v2 5/6] target/riscv: update APLIC and IMSIC to support KVM AIA

- Do not set the mmio operations of APLIC and IMSIC when using KVM AIA - Send interrupt signal to KVM AIA via KVM_IRQ_LINE API Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- hw/intc/riscv_aplic.c | 19 +++ hw/intc/riscv_imsic.c | 16 +++- 2 files changed, 26

[PTACH v2 4/6] target/riscv: Create an KVM AIA irqchip

implement a function to create an KVM AIA chip Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- target/riscv/kvm.c | 83 target/riscv/kvm_riscv.h | 3 ++ 2 files changed, 86 insertions(+) diff --git a/target/riscv/kvm.c b/target/riscv

[PTACH v2 2/6] target/riscv: support the AIA device emulateion with KVM enabled

Remove M mode AIA devices when using KVM acceleration Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- hw/riscv/virt.c | 198 +--- 1 file changed, 104 insertions(+), 94 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index

[PTACH v2 3/6] target/riscv: check the in-kernel irqchip support

We check the in-kernel irqchip support when using KVM acceleration. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- target/riscv/kvm.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 0f932a5b96..eb469e8ca5

[PTACH v2 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support

Update the linux headers to get the latest KVM RISC-V headers with AIA support by the scripts/update-linux-headers.sh. The linux headers is comes from the riscv_aia_v1 branch available at https://github.com/avpatel/linux.git. It hasn't merged into the mainline kernel. Signed-off-by: Yong

[PTACH v2 0/6] Add RISC-V KVM AIA Support

This series adds support for KVM AIA in RISC-V architecture. In order to test these patches, we require Linux with KVM AIA support which can be found in the qemu_kvm_aia branch at https://github.com/yong-xuan/linux.git This kernel branch is based on the riscv_aia_v1 branch available at https

[PATCH 2/6] target/riscv: support the AIA device emulateion with KVM enabled

Remove M mode AIA devices when using KVM acceleration Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- hw/riscv/virt.c | 204 +--- 1 file changed, 108 insertions(+), 96 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index

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