[RFC PATCH 3/5] hw/intc: Add Nuclei Systimer

This patch provides an implementation of Nuclei Systimer, which like clint. In MCU mode, It only work for hart-0. MultiCore support will run on 200t board for Linux. https://doc.nucleisys.com/nuclei_spec/isa/timer.html Signed-off-by: Wang Junqiang --- hw/intc/Kconfig | 3 +

[RFC PATCH 5/5] Nuclei FPGA Evaluation Kit MCU Machine

This patch provides an implementation of Nuclei FPGA Evaluation Kit Board as MCU mode. The Machine based on Nuclei's specification which has Customized register. The following machine is implemented: -"Nuclei 100T": SYSTIMER, ECLIC, UART ... Signed-off-by: Wang Junqiang --- default-configs/d

[RFC PATCH 1/5] target/riscv: Add Nuclei CSR and Update interrupt handling

This patch adds Nuclei CSR support for ECLIC and update the related interrupt handling. https://doc.nucleisys.com/nuclei_spec/isa/core_csr.html --- target/riscv/cpu.c | 25 +- target/riscv/cpu.h | 42 ++- target/riscv/cpu_bits.h | 37 ++

[RFC PATCH 4/5] hw/char: Add Nuclei Uart

This patch provides the initial implementation of Nuclei Uart which is opensource in Nuclei's Hummingbird Project. Signed-off-by: Wang Junqiang --- hw/char/Kconfig | 3 + hw/char/meson.build | 1 + hw/char/nuclei_uart.c | 208 ++

[RFC PATCH 2/5] hw/intc: Add Nuclei ECLIC device

This patch provides an implementation of Nuclei ECLIC Device. Nuclei processor core have been equipped with an Enhanced Core Local Interrupt Controller (ECLIC), which is optimized based on the RISC-V standard CLIC, to manage all interrupt sources. https://doc.nucleisys.com/nuclei_spec/isa/eclic.ht

[RFC PATCH 0/5] RISC-V:support Nuclei FPGA Evaluation Kit

wangjunqiang [1] https://doc.nucleisys.com/nuclei_sdk/design/board/nuclei_fpga_eval.html [2] https://doc.nucleisys.com/nuclei_spec/isa/eclic.html [3] https://doc.nucleisys.com/nuclei_spec/isa/core_csr.html [4] https://github.com/Nuclei-Software/nuclei-sdk.git [5] https://github.com/RT-Thread/rt-thread