u can make an exception and include
the attached patch into QEMU.
It would really help me continue to run QEMU on my legacy MacOS X 10.13
version.
Thanks in advance!
Kind regards,
Tobias Markus
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2314
Signed-off-by: Tobias Markus
--
Hi Ayan,
as far as I know, there is no board/SoC that uses the Cortex-R52 in Qemu
right now. If you want, I can try to find the one that I used
during development. I was able to run Zephyr in Qemu with that code.
Best regards,
Tobias
On 05.05.23 14:21, Ayan Kumar Halder wrote:
Hi Tobias
Thanks for all the help, I learned a lot!
Best regards,
Tobias
On 19.12.22 18:05, Peter Maydell wrote:
On Tue, 6 Dec 2022 at 10:25, wrote:
From: Tobias Röhmel
Sorry for the "Reviewed-by" messup. I missed that on the explanation
page. Thanks again for the review :)
v6:
patch 5
On 06.12.22 11:39, Philippe Mathieu-Daudé wrote:
On 6/12/22 11:24, tobias.roeh...@rwth-aachen.de wrote:
From: Tobias Röhmel
v6:
patch 5:
- I'm freeing the PRBAR/... strings explicitly now since
I don't know how to use autofree in this setup correctly.
Maybe {} around the
give it a shot in the coming days, but
it might take some time.
Side note: I found the 'missing' 12b in 12b of TCP options being added. :-| So
sorry for that noise.
With best regards,
Tobias
MTU1500
RTL8139: +++ C+ mode offloaded task TSO IP data 7272 frame data 7292 specified
MSS=14
Heho,
Thanks, will test the three patches later.
With best regards,
Tobias
-Original Message-
From: Stefan Hajnoczi
Sent: Thursday, 17 November 2022 17:57
To: Tobias Fiebig
Cc: Jason Wang ; Stefan Hajnoczi ;
qemu-devel@nongnu.org; qemu-sta...@nongnu.org; Russell King - ARM Linux
, to test how the real hardware
behaved?
With best regards,
Tobias
-Original Message-
From: Stefan Hajnoczi
Sent: Thursday, 17 November 2022 12:16
To: Tobias Fiebig
Cc: Jason Wang ; Stefan Hajnoczi ;
qemu-devel@nongnu.org; qemu-sta...@nongnu.org; Russell King - ARM Linux
Subject: Re
28 specified
MSS=1000
# MSS_requested=600
RTL8139: +++ C+ mode offloaded task TSO IP data 1796 frame data 1816 specified
MSS=600
With best regards,
Tobias
diff --git a/hw/net/rtl8139.c b/hw/net/rtl8139.c
index e6643e3c9d..59321460b9 100644
--- a/hw/net/rtl8139.c
+++ b/hw/net/rtl8139
Us (in case that works with the rtl8139).
Sidenote: This all seems to be a non-issue for v6, as the RTL8139 does not
support TSO for v6, so at least one thing less to worry about. ;-)
With best regards,
Tobias
ill give this a shot later on and let you know.
With best regards,
Tobias
uld have some brainspace for this tomorrow
night (UTC) again.
With best regards,
Tobias
doesn't show an effect, I'll hold tcpdump to the wire again.
With best regards,
Tobias
-Original Message-
From: Stefan Hajnoczi
Sent: Tuesday, 15 November 2022 17:37
To: qemu-devel@nongnu.org
Cc: jasow...@redhat.com; qemu-sta...@nongnu.org; Stefan Hajnoczi
; Russell King - A
Thank you very much for the review!
I have a few questions:
On 27.09.22 15:50, Peter Maydell wrote:
On Sat, 20 Aug 2022 at 15:19, wrote:
From: Tobias Röhmel
Signed-off-by: Tobias Röhmel
---
target/arm/cpu.h| 10 +++
target/arm/helper.c | 171
On 18.07.22 13:54, Tobias Roehmel wrote:
v2:
PATCH 1:
I have left the flag in for now because there there is a lot of use for it in
the MPU translation code.
The PMSAv8r differs in quite a view ways from the implementation in the
Cortex-M. I think using
!ARM_FEATURE_M in all of those cases
From: Tobias Röhmel
Add PMSAv8r translation that is used by the ARM Cortex-R52.
Signed-off-by: Tobias Röhmel
---
target/arm/ptw.c | 171 +--
1 file changed, 150 insertions(+), 21 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index
From: Tobias Röhmel
Add ARMCacheAttrs to the signature of pmsav8_mpu_lookup to prepare for the
Cortex-R52 MPU which uses and combines cache attributes of different
translation levels.
Signed-off-by: Tobias Röhmel
---
target/arm/internals.h | 13 +++--
target/arm/m_helper.c | 3
From: Tobias Röhmel
This flag is necessary to add features for the Cortex-R52.
Signed-off-by: Tobias Röhmel
---
target/arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index df677b2d5d..86e06116a9 100644
--- a/target/arm/cpu.h
+++ b/target/arm
From: Tobias Röhmel
All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3
Signed-off-by: Tobias Röhmel
---
target/arm/cpu_tcg.c | 42 ++
1 file changed, 42 insertions(+)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
From: Tobias Röhmel
The Cortex-R52 has a 2 stage MPU translation process but doesn't have the
FEAT_S2FWB feature. This makes it neccessary to allow for the old cache
attribut combination.
This is facilitated by changing the control path of combine_cacheattrs instead
of failing if the s
From: Tobias Röhmel
Cortex-R52 has the MPUIR register which has the same encoding
has the MIDR alias with opc2=4. So we only add that alias
when we are not realizing a Cortex-R.
Signed-off-by: Tobias Röhmel
---
target/arm/helper.c | 12 +---
1 file changed, 9 insertions(+), 3
From: Tobias Röhmel
ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even
tough they don't have the TTBCR register.
See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R
AArch32 architecture profile Version:A.c section C1.2.
Signed-off-by: Tobias Röhmel
---
t
From: Tobias Röhmel
Signed-off-by: Tobias Röhmel
---
target/arm/cpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 1b5d535788..9007768418 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -258,6 +258,10 @@ static void
onality that is not implemented:
- Changing between single and double precision floats
- Some hypervisor related functionality (HCR.T(R)VM,HADFSR,...)
Tobias Röhmel (9):
target/arm: Add ARM_FEATURE_V8_R
target/arm: Don't add all MIDR aliases for Cortex-R
target/arm: Make RVBAR availabl
From: Tobias Röhmel
Signed-off-by: Tobias Röhmel
---
target/arm/cpu.h| 10 +++
target/arm/helper.c | 171
2 files changed, 181 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 86e06116a9..632d0d13c6 100644
--- a/target/arm
From: Tobias Röhmel
The Cortex-R52 can access SPSR_hyp from hypervisor mode
as discussed here: https://github.com/zephyrproject-rtos/zephyr/issues/47330
Signed-off-by: Tobias Röhmel
---
target/arm/op_helper.c | 8
target/arm/translate.c | 5 +++--
2 files changed, 11 insertions(+), 2
From: Tobias Röhmel
The Cortex-R52 has a 2 stage MPU translation process but doesn't have the
FEAT_S2FWB feature. This makes it neccessary to allow for the old cache
attribut combination.
This is facilitated by changing the control path of combine_cacheattrs instead
of failing if the s
From: Tobias Röhmel
Enable TTBCR_EAE during reset since it's always set to 1 for Cortex-R52.
See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R
AArch32 architecture profile Version:A.c section C1.2.
Signed-off-by: Tobias Röhmel
---
target/arm/cpu.c | 3 +++
1
r1p3
- ARM Architecture Reference Manual Supplement
-ARMv8 for the ARMv8-R AArch32 architecture profile Version A.c
Functionality that is not implemented:
- Changing between single and double precision floats
- Some hypervisor related functionality (HCR.T(R)VM,HADFSR,...)
Tobias Röhmel (11
From: Tobias Röhmel
This register is used by the ARM Cortex-R52.
Signed-off-by: Tobias Röhmel
---
target/arm/helper.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 6457e6301c..bdf1df37d5 100644
--- a/target
From: Tobias Röhmel
Signed-off-by: Tobias Röhmel
---
configs/devices/arm-softmmu/default.mak | 1 +
hw/arm/Kconfig | 5 +
hw/arm/meson.build | 1 +
hw/arm/r52_machine.c| 133 +++
hw/arm/r52_virt.c
From: Tobias Röhmel
All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3
Signed-off-by: Tobias Röhmel
---
target/arm/cpu_tcg.c | 54
1 file changed, 54 insertions(+)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
From: Tobias Röhmel
Signed-off-by: Tobias Röhmel
---
target/arm/cpu.h| 10 +++
target/arm/helper.c | 171
2 files changed, 181 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 86e06116a9..632d0d13c6 100644
--- a/target/arm
From: Tobias Röhmel
Add PMSAv8r translation that is used by the ARM Cortex-R52.
Signed-off-by: Tobias Röhmel
---
target/arm/ptw.c | 171 +--
1 file changed, 150 insertions(+), 21 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index
From: Tobias Röhmel
The ARM Cortex-R52 is not AARCH64 but uses RVBAR.
Signed-off-by: Tobias Röhmel
---
target/arm/cpu.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 1b5d535788..2c26a5387d 100644
--- a/target/arm/cpu.c
From: Tobias Röhmel
Add ARMCacheAttrs to the signature of pmsav8_mpu_lookup to prepare for the
Cortex-R52 MPU which uses and combines cache attributes of different
translation levels.
Signed-off-by: Tobias Röhmel
---
target/arm/internals.h | 13 +++--
target/arm/m_helper.c | 3
From: Tobias Röhmel
This flag is necessary to add features for the Cortex-R52.
Signed-off-by: Tobias Röhmel
---
target/arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index df677b2d5d..86e06116a9 100644
--- a/target/arm/cpu.h
+++ b/target/arm
`,
performing the range check against the actual size of the target address
space. It also moves the corresponding block to prevent it from being
called incorrectly when the mapping itself fails.
Signed-off-by: Tobias Koch
---
linux-user/mmap.c | 21 -
1 file changed, 12
Public bug reported:
When using...
a) Intel virtualized graphics (iGVT-g) with dmabuf output
b) QEMU's GTK display with GL output enabled (-display gtk,gl=on)
c) A Wayland compositor (Sway in my case)
a segfault occurs at some point on boot (I guess as soon as the guest starts
using the virtua
Ping
On 6/16/20 12:10 AM, Tobias Koch wrote:
> Ok, so according to the manpage, mremap generates EFAULT when "the range
> old_address to old_address+old_size is an
> invalid virtual memory address for this process". This is what the kernel
> does for the stack guard. Howe
to be
special-cased to fake kernel behavior.
I'm open to other suggestions. I also understand that the code duplication in
elfload.c and mmap.c to handle this is
undesirable, but the most viable alternative seems to be introducing more
globals.
On 6/15/20 11:28 PM, Tobias Koch wrote:
> Hm,
Hm, I see I need to have another look at this :)
On 6/15/20 10:17 AM, Tobias Koch wrote:
> Hi Laurent,
>
> the code in musl libc probing the stack is in
>
> https://git.musl-libc.org/cgit/musl/plain/src/thread/pthread_getattr_np.c
>
> The setup in elfload.c doe
à 22:05, Tobias Koch a écrit :
>> If the address range starting at old_address overlaps with the stack guard it
>> is invalid and mremap must fail with EFAULT. The musl c library relies on
>> this
>> behavior to detect the stack size, which it does by doing consecutive mremaps
Thanks a lot for looking into it!
Yes, we were able to verify that this patch does fix the problem.
Many thanks!
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https://bugs.launchpad.net/bugs/1870098
Title:
[block/vpc] dynamic d
Ah, sorry, I failed to mention this: Due to this bug, qemu currently
cannot create VHDs that are suitable for upload to Azure (because Azure
expects disks that are aligned exactly to 1MB).
If it would not be too much trouble for you to submit the patch, I would
appreciate that a lot. I've never su
Public bug reported:
In current qemu versions (observed in 5.0.0-rc1 as well as
2833ad487cfff7dc33703e4731b75facde1c561e), disk headers for dynamic VPCs
are written with an incorrect "block allocation table entries" value.
https://www.microsoft.com/en-us/download/details.aspx?id=23850 (the
corres
(such as the Ruby
interpreter) that calls pthread_getattr_np under musl will crash on 32 bit
targets emulated on a 64 bit host.
Signed-off-by: Tobias Koch
---
linux-user/mmap.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/linux-user/mmap.c b/linux-user/mmap.c
index
Analogous to what commit 5dfa88f7 did for setrlimit, this commit
selectively ignores limits for memory-related resources in prlimit64
calls. This is to prevent too restrictive limits from causing QEMU
itself to malfunction.
Signed-off-by: Tobias Koch
---
linux-user/syscall.c | 5 -
1 file
Analogous to what commit 5dfa88f7 did for setrlimit, this commit
selectively ignores limits for memory-related resources in prlimit64
calls. This is to prevent too restrictive limits from causing QEMU
itself to malfunction.
Signed-off-by: Tobias Koch
---
linux-user/syscall.c | 16
I carried out the following test:
* fetched the QEMU coming with 18.04,
* added this patch,
* built an LXD container with arch arm64 and the patched qemu-aarch64-static
inside,
* launched it on amd64
Previously various systemd services would not come up properly, now they
are running like a char
Thanks, Laurent! I'll get back to you, asap.
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https://bugs.launchpad.net/bugs/1823790
Title:
QEMU mishandling of SO_PEERSEC forces systemd into tight loop
Status in QEMU:
Confirmed
** Changed in: qemu
Status: New => Confirmed
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https://bugs.launchpad.net/bugs/1823790
Title:
QEMU mishandling of SO_PEERSEC forces systemd into tight loop
Status in QEMU:
Con
I'm a bit surprised that this bug doesn't get more attention, as it
makes it very hard to run qemu-emulated containers of Bionic hosted on
Bionic. Running such containers is a common way to cross-compile
packages for foreign architectures in the absence of sufficiently
powerful target HW.
The docu
On 2019-01-29 at 11:19:02 +0100, Peter Maydell wrote:
> On Tue, 29 Jan 2019 at 09:51, Tobias Klauser wrote:
> >
> > Add the Altera JTAG UART model.
> >
> > Hardware emulation based on:
> > https://www.altera.com/en_US/pdfs/literature/ug/ug_embedded_ip.pdf
>
Add the Altera JTAG UART model.
Hardware emulation based on:
https://www.altera.com/en_US/pdfs/literature/ug/ug_embedded_ip.pdf
(Please see "Register Map" on page 65)
Signed-off-by: Juro Bystricky
Acked-by: Marek Vasut
Tested-by: Tobias Klauser
Signed-off-by: Tobias Klauser
---
Re
The errors still keep appearing. The mcelog still shows the exact errors
posted in the very fist comment.
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https://bugs.launchpad.net/bugs/1307225
Title:
Running a virtual machine on a
Last time I saw this error in my mcelog was in August. Probably, some
update fixed it. I'll check the next days/weeks if I still see it. This
is a quite long time, at the time of my original bug report, I got the
errors multiple times a day and later multiple times a week.
About the workaround mov
From: Juro Bystricky
Add the Altera JTAG UART model.
Hardware emulation based on:
https://www.altera.com/en_US/pdfs/literature/ug/ug_embedded_ip.pdf
(Please see "Register Map" on page 65)
Signed-off-by: Juro Bystricky
Acked-by: Marek Vasut
Tested-by: Tobias Klauser
[tk: updated
ff-by: Tobias Schramm
---
v5: Eliminate expandable variables, check mandatory commandline options
first
v4: Use OPT_NUMBER for file mode arguments, fix back to front naming,
fix resource leak and add sanity checking for fmode/dmode arguments
v3: Use unsigned types for umask
v2: Adjust
good idea. Considering
that it is used in quite a few places might it be a good idea to write a macro
for that check?
Also I have added a much more descriptive commit message.
Again, thank you for the great help (and patience :)).
Regards,
Tobias Schramm
Tobias Schramm (1):
9pfs: local: Add s
Signed-off-by: Tobias Schramm
---
v4: Use OPT_NUMBER for file mode arguments, fix back to front naming,
fix resource leak and add sanity checking for fmode/dmode arguments
v3: Use unsigned types for umask
v2: Adjust patch to QEMU code style
fsdev/file-op-9p.h | 4
fsdev/qemu
dup if an error during parsing
of fmode/dmode
occurred.
Thanks to Greg Kurz for pointing out most of the above issues to me.
Tobias Schramm
Tobias Schramm (1):
Add support for custom fmode/dmode in 9ps mapped security modes
fsdev/file-op-9p.h | 4
fsdev/qemu-fsdev-opts.c | 12 ++
Hi,
as per Manos suggestion I'm now parsing the fmask/dmask as unsigned rather than
signed longs.
Tobias Schramm
Tobias Schramm (1):
Add support for custom fmasks/dmasks in 9ps mapped mode
fsdev/file-op-9p.h | 4
fsdev/qemu-fsdev-opts.c | 12
hw/9pfs/9p-lo
Signed-off-by: Tobias Schramm
---
v3: Use unsigned types for umask
v2: Adjust patch to QEMU code style
fsdev/file-op-9p.h | 4
fsdev/qemu-fsdev-opts.c | 12
hw/9pfs/9p-local.c | 29 +
hw/9pfs/9p.c| 3 +++
4 files changed
Hi,
as suggested by the automated tests I adjusted the code style to be
compatible with QEMUs existing code base.
The previous failed test seems to be irrelevant since it passes fine on my dev
machine and the failure is in a totally unrelated component.
Tobias Schramm
Tobias Schramm (1):
Add
Signed-off-by: Tobias Schramm
---
v2: Adjust patch to QEMU code style
fsdev/file-op-9p.h | 4
fsdev/qemu-fsdev-opts.c | 12
hw/9pfs/9p-local.c | 29 +
hw/9pfs/9p.c| 3 +++
4 files changed, 44 insertions(+), 4 deletions
Signed-off-by: Tobias Schramm
---
fsdev/file-op-9p.h | 4
fsdev/qemu-fsdev-opts.c | 12
hw/9pfs/9p-local.c | 33 +
hw/9pfs/9p.c| 3 +++
4 files changed, 48 insertions(+), 4 deletions(-)
diff --git a/fsdev/file-op-9p.h b
ctual permissions of newly created files and
folders on
the host. This is my first patch for QEMU. Please let me know if there are any
issues with
it.
Tobias Schramm
Tobias Schramm (1):
Add support for custom fmasks/dmasks in 9ps mapped mode
fsdev/file-op-9p.h | 4
fsdev/qemu-
ith console on Altera JTAG
UART with "qemu-system-nios2 -M 10m50-ghrd" using this patch.
Feel free to add my
Tested-by: Tobias Klauser
> diff --git a/hw/char/altera_juart.c b/hw/char/altera_juart.c
[...]
> +static const VMStateDescription vmstate_altera_juart = {
> +
client is connected the audio transmission is successful for a
few seconds, but the server drops the connection after that and refuses to take
new connections.
Please let me know, if you need more information. I'll gladly provide
strace or valgrind logs.
Best regards,
Tobias
To m
ide
strace or valgrind logs.
Best regards,
Tobias
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1619896/+subscriptions
a
few seconds, but the server drops the connection after that and refuses to take
new connections.
Please let me know, if you need more information. I'll gladly provide
strace or valgrind logs.
Best regards,
Tobias
** Affects: qemu
Importance: Undecided
Status: New
** Tags
On Sun, 8 Mar 2015 21:53:30 +0900
Peter Maydell wrote:
> On 8 March 2015 at 21:37, Tobias Nygren wrote:
> > On Sun, 8 Mar 2015 19:27:27 +0900
> > Peter Maydell wrote:
> >> Does NetBSD have a big stack of out-of-tree patches for QEMU,
> >> or do you run basicall
Hello,
On Sun, 8 Mar 2015 19:27:27 +0900
Peter Maydell wrote:
> On 6 March 2015 at 06:37, Tobias Nygren wrote:
> > A couple of #ifdef changes necessary to use NetBSD's ucontext
> > structs on sparc64 and arm.
> >
> > Signed-off-by: Tobias Nygren
>
>
A couple of #ifdef changes necessary to use NetBSD's ucontext
structs on sparc64 and arm.
Signed-off-by: Tobias Nygren
---
user-exec.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/user-exec.c b/user-exec.c
index 1ff8673..8f57e8a 100644
--- a/user-e
Hello Paolo,
yes, i booted my old windows7-vm which used seabios, and it also crashed
with the same Suberror: 1;
In the meantime i tested 3.18-rc3 - this works perfectly, i guess your
fix is already in there?
Greetings
Tobias
Am 2014-11-04 16:05, schrieb Paolo Bonzini:
On 22/10/2014 14
?
Is this the right mailinglist, or is a kvm Mailinglist better?
Greetings
Tobias
So, at least, this does not seem to be something to worry about. But
anyways, why does it only happen if a virtual machine is executed?
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Title:
On 2014-09-24 at 11:09:42 +0200, Peter Maydell wrote:
> On 24 September 2014 00:58, Michael Tokarev wrote:
> > 18.09.2014 21:25, Tobias Klauser wrote:
> >> ATTRIBUTE_UNUSED is already defined in disas/bfd.h, which is included.
> >> Thus, there is no need to redefine it
On 2014-09-24 at 09:58:45 +0200, Michael Tokarev wrote:
> 18.09.2014 21:25, Tobias Klauser wrote:
> > ATTRIBUTE_UNUSED is already defined in disas/bfd.h, which is included.
> > Thus, there is no need to redefine it.
>
> Is there any harm in keeping it here?
No.
&
ATTRIBUTE_UNUSED is already defined in disas/bfd.h, which is included.
Thus, there is no need to redefine it.
Signed-off-by: Tobias Klauser
---
disas/arm.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/disas/arm.c b/disas/arm.c
index 76e97a8..6f63406 100644
--- a/disas/arm.c
+++ b/disas
>From Documentation/x86/x86_64/boot-options.txt:
mce=bootlog
Enable logging of machine checks left over from booting.
Disabled by default on AMD because some BIOS leave bogus ones.
If your BIOS doesn't do that it's a good idea to enable though
to make sure you lo
Running the VM with "-cpu Haswell" set still causes those "Internal
Parity Errors", but not so many …
** Description changed:
I'm running a virtual Windows SBS 2003 installation on a Xeon E3 Haswell
system running Gentoo Linux. First, I used Qemu 1.5.3 (the latest stable
version on Gentoo).
Still happens with qemu 2.0.0 and the same environment (Windows SBS 2003
32 bit guest on a Gentoo Linux amd64 Haswell host).
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https://bugs.launchpad.net/bugs/1307225
Title:
Running a v
** Description changed:
I'm running a virtual Windows SBS 2003 installation on a Xeon E3 Haswell
system running Gentoo Linux. First, I used Qemu 1.5.3 (the latest stable
version on Gentoo). I got a lot of machine check events ("mce: [Hardware
Error]: Machine check events logged") in dmesg
** Description changed:
I'm running a virtual Windows SBS 2003 installation on a Xeon E3 Haswell
system running Gentoo Linux. First, I used Qemu 1.5.3 (the latest stable
version on Gentoo). I got a lot of machine check events ("mce: [Hardware
Error]: Machine check events logged") in dmesg
Public bug reported:
I'm running a virtual Windows SBS 2003 installation on a Xeon E3 Haswell
system running Gentoo Linux. First, I used Qemu 1.5.3 (the latest stable
version on Gentoo). I got a lot of machine check events ("mce: [Hardware
Error]: Machine check events logged") in dmesg that always
Did some testing: if one pauses the vms that run windows before suspending
ubuntu no high cpu usage is there once the host and windows vms are resumed.
for me it's workable then in ubuntu by using a suspend / resume script with
power manaager. I put this in /etc/pm/sleep.d (and make it executabl
Hi,
ok confusion cleared :-)
actually i only have this issue with windows guests. linux guests do not
show a high cpu usage after suspend resume.
so are there any recommendations you would have to work around it ?
regards,
Tobias.
On 18-10-13 09:42, mike wrote:
> On 10/18/2013 03:41
Hello MIke,
but this concerns a windows guest. you mean a kernel configuration
within the guest (aka recompile ?) or a boot parameter within the guest ?
regards,
Tobias.
On 18-10-13 09:26, mike wrote:
> On 10/18/2013 03:12 PM, tobias wrote:
>> Hello Mike,
>>
>> Thanks a
Hello Mike,
Thanks a lot for getting back on this.
Is the "cpu idle driver" a command line option I need to specify for
qemu (the -cpu option ?)
I could not find a reference to "idle" in the man page.
regards,
Tobias.
On 18-10-13 04:33, mike wrote:
On 10/18/2013 04:29 A
hi,
tried your option but it does not help. (cpu usage is still high)
below my command line syntax:
qemu-system-x86_64 -global mc146818rtc.lost_tick_policy=slew -machine
accel=kvm:tcg -name win7 -S -machine pc-i440fx-1.4,accel=kvm,usb=off -m 2048
-realtime mlock=off -smp 1,sockets=1,cores=1,thre
Hi,
I am also encountering the bug of high cpu usage for a windows guest after
suspend resume of my ubuntu host. Problem was in 13.04 but it's also still
there in 13.10.
The windows guest has virtio / spice enabled.
Linux guests do not get the high cpu usage.
Are there any more logs required or
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PING
(Mail resent - sorry, Thunderbird wrapped line in the first mail)
PS: Sorry for the two wrapped lines below ---, but probably not worth
resending the patch just for that.
On 08/25/2013 12:20 PM, Tobias Markus wrote:
> When in Long M
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On 08/25/2013 12:20 PM, Tobias Markus wrote:
> When in Long Mode, cpu_x86_seg_cache() logs "DS16" because the
> Default operation size bit (D/B bit) is not set for Long Mode Data
> Segments since there are only Data Segments
bit of the hidden
flags variable and logging "DS" if it is set. (I.e. in Long Mode all Data
Segments are logged as "DS")
Signed-off-by: Tobias Markus
---
v3: * Manually Break Lines
* Again change line wrapping as suggested by Eric Blake
v2: * Fix line wrapping as suggested in
On 08/23/2013 10:01 PM, Richard Henderson wrote:
> On 08/23/2013 12:09 PM, Tobias Markus wrote:
>> When in Long Mode, cpu_x86_seg_cache() logs "DS16" because the Default
>> operation size bit (D/B bit) is not set for Long Mode Data Segments since
>> there are only
bit of the hidden flags
variable and logging "DS" if it is set. (I.e. in Long Mode all Data Segments
are logged as "DS")
Signed-off-by: Tobias Markus
---
v2: * Fix line wrapping as suggested in IRC
* Break the line
Note that alternatively, Data Segments in Long Mode could
bit of the hidden
flags variable and logging "DS" if it is set, i.e. in Long Mode all Data
Segments are logged as "DS".
Signed-off-by: Tobias Markus
---
Note that alternatively, Data Segments in Long Mode could be logged as
"DS64" to avoid confusion about the missing
ory.c:1378:
memory_region_del_subregion: Assertion `subregion->parent == mr' failed.
Waiting for data...
Am 20.02.2012 18:08, schrieb Anthony PERARD:
On Mon, Feb 20, 2012 at 16:11, Tobias Geiger wrote:
My Domu (Win7_64) boots fine, but 2 of my 6 passed-through pcidevices dont get
passed through at
itional).
Anything i can do to debug this further?
Greetings
Tobias
Am Montag, 20. Februar 2012, 12:31:52 schrieb Anthony PERARD:
> On Mon, Feb 20, 2012 at 10:51, Tobias Geiger
wrote:
> > i wanted to test these patches against
> > http://xenbits.xensource.com/xen-unstable.hg but it seems
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