From: qianfan Zhao
Types of memory that the SDRAM controller supports are DDR2/DDR3
and capacities of up to 2GiB. This commit adds emulation support
of the Allwinner R40 SDRAM controller.
This driver only support 256M, 512M and 1024M memory now.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinne
From: qianfan Zhao
R40 has two ethernet controllers named as emac and gmac. The emac is
compatibled with A10, and the GMAC is compatibled with H3.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 50 --
hw/arm/bananapi_m2u.c | 3 ++
inc
From: qianfan Zhao
Add test case for booting from initrd and sd card.
Signed-off-by: qianfan Zhao
Reviewed-by: Niek Linnenbank
Tested-by: Niek Linnenbank
---
tests/avocado/boot_linux_console.py | 176
1 file changed, 176 insertions(+)
diff --git a/tests/avocado/
From: qianfan Zhao
TWI(i2c) is designed to be used as an interface between CPU host and the
serial 2-Wire bus. It can support all standard 2-Wire transfer, can be
operated in standard mode(100kbit/s) or fast-mode, supporting data rate
up to 400kbit/s.
Signed-off-by: qianfan Zhao
Reviewed-by: Ni
From: qianfan Zhao
This patch adds minimal support for AXP-221 PMU and connect it to
bananapi M2U board.
Signed-off-by: qianfan Zhao
---
hw/arm/Kconfig| 3 +-
hw/arm/bananapi_m2u.c | 6 +
hw/misc/Kconfig | 2 +-
hw/misc/axp209.c | 238 --
From: qianfan Zhao
Add documents for Banana Pi M2U
Signed-off-by: qianfan Zhao
Reviewed-by: Niek Linnenbank
---
docs/system/arm/bananapi_m2u.rst | 138 +++
1 file changed, 138 insertions(+)
create mode 100644 docs/system/arm/bananapi_m2u.rst
diff --git a/docs/sys
From: qianfan Zhao
R40 has eight UARTs, support both 16450 and 16550 compatible modes.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 34 +++---
include/hw/arm/allwinner-r40.h | 8
2 files changed, 39 insertions(+), 3 deletions(-)
diff -
From: qianfan Zhao
***History***
# v1: 2023-03-21
The first version which add allwinner-r40 support, supported features:
+ ccu
+ dram controller
+ uart
+ i2c and pmic(axp221)
+ sdcard
+ emac/gmac
Also provide a test case under avocado, running quickly test:
$ AVOCADO_ALLOW_LARGE_STORAGE=yes t
From: qianfan Zhao
Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
and a Mali400 MP2 GPU from ARM. It's also known as the Allwinner T3
for In-Car Entertainment usage, A40i and A40pro are variants that
differ in applicable temperatures range (industrial and military).
Signed-off
From: qianfan Zhao
A64's sd register was similar to H3, and it introduced a new register
named SAMP_DL_REG location at 0x144. The dma descriptor buffer size of
mmc2 is only 8K and the other mmc controllers has 64K.
Also fix allwinner-r40's mmc controller type.
Signed-off-by: qianfan Zhao
---
From: qianfan Zhao
Only a few important registers are added, especially the SRAM_VER
register.
Signed-off-by: qianfan Zhao
Reviewed-by: Niek Linnenbank
---
hw/arm/Kconfig| 1 +
hw/arm/allwinner-r40.c| 7 +-
hw/misc/Kconfig | 3 +
hw/misc
From: qianfan Zhao
The CCU provides the registers to program the PLLs and the controls
most of the clock generation, division, distribution, synchronization
and gating.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: qian
From: qianfan Zhao
TWI(i2c) is designed to be used as an interface between CPU host and the
serial 2-Wire bus. It can support all standard 2-Wire transfer, can be
operated in standard mode(100kbit/s) or fast-mode, supporting data rate
up to 400kbit/s.
Signed-off-by: qianfan Zhao
---
hw/arm/all
From: qianfan Zhao
Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
and a Mali400 MP2 GPU from ARM. It's also known as the Allwinner T3
for In-Car Entertainment usage, A40i and A40pro are variants that
differ in applicable temperatures range (industrial and military).
Signed-off
From: qianfan Zhao
A64's sd register was similar to H3, and it introduced a new register
named SAMP_DL_REG location at 0x144. The dma descriptor buffer size of
mmc2 is only 8K and the other mmc controllers has 64K.
Also fix allwinner-r40's mmc controller type.
Signed-off-by: qianfan Zhao
---
From: qianfan Zhao
Types of memory that the SDRAM controller supports are DDR2/DDR3
and capacities of up to 2GiB. This commit adds emulation support
of the Allwinner R40 SDRAM controller.
This driver only support 256M, 512M and 1024M memory now.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinne
From: qianfan Zhao
*** history ***
# v1: 2023-03-21
The first version which add allwinner-r40 support, supported features:
+ ccu
+ dram controller
+ uart
+ i2c and pmic(axp221)
+ sdcard
+ emac/gmac
Also provide a test case under avocado, running quickly test:
$ AVOCADO_ALLOW_LARGE_STORAGE=y
From: qianfan Zhao
This patch adds minimal support for AXP-221 PMU and connect it to
bananapi M2U board.
Signed-off-by: qianfan Zhao
---
hw/arm/Kconfig| 3 +-
hw/arm/bananapi_m2u.c | 6 +
hw/misc/Kconfig | 2 +-
hw/misc/axp209.c | 238 --
From: qianfan Zhao
Add documents for Banana Pi M2U
Signed-off-by: qianfan Zhao
---
docs/system/arm/bananapi_m2u.rst | 138 +++
1 file changed, 138 insertions(+)
create mode 100644 docs/system/arm/bananapi_m2u.rst
diff --git a/docs/system/arm/bananapi_m2u.rst b/doc
From: qianfan Zhao
The CCU provides the registers to program the PLLs and the controls
most of the clock generation, division, distribution, synchronization
and gating.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: qian
From: qianfan Zhao
Add test case for booting from initrd and sd card.
Signed-off-by: qianfan Zhao
---
tests/avocado/boot_linux_console.py | 176
1 file changed, 176 insertions(+)
diff --git a/tests/avocado/boot_linux_console.py
b/tests/avocado/boot_linux_console.
From: qianfan Zhao
R40 has eight UARTs, support both 16450 and 16550 compatible modes.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 31 ---
include/hw/arm/allwinner-r40.h | 8
2 files changed, 36 insertions(+), 3 deletions(-)
diff --gi
From: qianfan Zhao
Only a few important registers are added, especially the SRAM_VER
register.
Signed-off-by: qianfan Zhao
---
hw/arm/Kconfig| 1 +
hw/arm/allwinner-r40.c| 7 +-
hw/misc/Kconfig | 3 +
hw/misc/allwinner-sramc.c | 1
From: qianfan Zhao
R40 has two ethernet controllers named as emac and gmac. The emac is
compatibled with A10, and the GMAC is compatibled with H3.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 50 --
hw/arm/bananapi_m2u.c | 3 ++
inc
From: qianfan Zhao
Add documents for Banana Pi M2U
Signed-off-by: qianfan Zhao
---
docs/system/arm/bananapi_m2u.rst | 138 +++
1 file changed, 138 insertions(+)
create mode 100644 docs/system/arm/bananapi_m2u.rst
diff --git a/docs/system/arm/bananapi_m2u.rst b/doc
From: qianfan Zhao
*** history ***
# v1: 2023-03-21
The first version which add allwinner-r40 support, supported features:
+ ccu
+ dram controller
+ uart
+ i2c and pmic(axp221)
+ sdcard
+ emac/gmac
Also provide a test case under avocado, running quickly test:
$ AVOCADO_ALLOW_LARGE_STORAGE=ye
From: qianfan Zhao
Only a few important registers are added, especially the SRAM_VER
register.
Signed-off-by: qianfan Zhao
---
hw/arm/Kconfig| 1 +
hw/arm/allwinner-r40.c| 7 +-
hw/misc/Kconfig | 3 +
hw/misc/allwinner-sramc.c | 1
From: qianfan Zhao
A64's sd register was similar to H3, and it introduced a new register
named SAMP_DL_REG location at 0x144. The dma descriptor buffer size of
mmc2 is only 8K and the other mmc controllers has 64K.
Also fix allwinner-r40's mmc controller type.
Signed-off-by: qianfan Zhao
---
From: qianfan Zhao
Add test case for booting from initrd and sd card.
Signed-off-by: qianfan Zhao
---
tests/avocado/boot_linux_console.py | 176
1 file changed, 176 insertions(+)
diff --git a/tests/avocado/boot_linux_console.py
b/tests/avocado/boot_linux_console.
From: qianfan Zhao
TWI(i2c) is designed to be used as an interface between CPU host and the
serial 2-Wire bus. It can support all standard 2-Wire transfer, can be
operated in standard mode(100kbit/s) or fast-mode, supporting data rate
up to 400kbit/s.
Signed-off-by: qianfan Zhao
---
hw/arm/all
From: qianfan Zhao
Types of memory that the SDRAM controller supports are DDR2/DDR3
and capacities of up to 2GiB. This commit adds emulation support
of the Allwinner R40 SDRAM controller.
This driver only support 256M, 512M and 1024M memory now.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinne
From: qianfan Zhao
This patch adds minimal support for AXP-221 PMU and connect it to
bananapi M2U board.
Signed-off-by: qianfan Zhao
---
hw/arm/Kconfig| 3 +-
hw/arm/bananapi_m2u.c | 6 +
hw/misc/Kconfig | 2 +-
hw/misc/axp209.c | 238 --
From: qianfan Zhao
R40 has two ethernet controllers named as emac and gmac. The emac is
compatibled with A10, and the GMAC is compatibled with H3.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 50 --
hw/arm/bananapi_m2u.c | 3 ++
inc
From: qianfan Zhao
R40 has eight UARTs, support both 16450 and 16550 compatible modes.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 31 ---
include/hw/arm/allwinner-r40.h | 8
2 files changed, 36 insertions(+), 3 deletions(-)
diff --gi
From: qianfan Zhao
Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
and a Mali400 MP2 GPU from ARM. It's also known as the Allwinner T3
for In-Car Entertainment usage, A40i and A40pro are variants that
differ in applicable temperatures range (industrial and military).
Signed-off
From: qianfan Zhao
The CCU provides the registers to program the PLLs and the controls
most of the clock generation, division, distribution, synchronization
and gating.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: qian
From: qianfan Zhao
Add documents for Banana Pi M2U
Signed-off-by: qianfan Zhao
---
docs/system/arm/bananapi_m2u.rst | 138 +++
1 file changed, 138 insertions(+)
create mode 100644 docs/system/arm/bananapi_m2u.rst
diff --git a/docs/system/arm/bananapi_m2u.rst b/doc
From: qianfan Zhao
Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
and a Mali400 MP2 GPU from ARM. It's also known as the Allwinner T3
for In-Car Entertainment usage, A40i and A40pro are variants that
differ in applicable temperatures range (industrial and military).
This patch
From: qianfan Zhao
Add documents for Banana Pi M2U
Signed-off-by: qianfan Zhao
---
docs/system/arm/bananapi_m2u.rst | 138 +++
1 file changed, 138 insertions(+)
create mode 100644 docs/system/arm/bananapi_m2u.rst
diff --git a/docs/system/arm/bananapi_m2u.rst b/doc
From: qianfan Zhao
R40 has SAMP_DL_REG register and mmc2 controller has only 8K dma buffer.
Fix it's compatible string.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c
ind
From: qianfan Zhao
This patch adds minimal support for AXP-221 PMU and connect it to
bananapi M2U board.
Signed-off-by: qianfan Zhao
---
hw/arm/Kconfig| 3 +-
hw/arm/bananapi_m2u.c | 6 +
hw/misc/Kconfig | 2 +-
hw/misc/axp209.c | 238 --
From: qianfan Zhao
Add test case for booting from initrd and sd card.
Signed-off-by: qianfan Zhao
---
tests/avocado/boot_linux_console.py | 176
1 file changed, 176 insertions(+)
diff --git a/tests/avocado/boot_linux_console.py
b/tests/avocado/boot_linux_console.
From: qianfan Zhao
Types of memory that the SDRAM controller supports are DDR2/DDR3
and capacities of up to 2GiB. This commit adds emulation support
of the Allwinner R40 SDRAM controller.
This driver only support 256M, 512M and 1024M memory now.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinne
From: qianfan Zhao
R40 has two ethernet controllers named as emac and gmac. The emac is
compatibled with A10, and the GMAC is compatibled with H3.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 50 --
hw/arm/bananapi_m2u.c | 3 ++
inc
From: qianfan Zhao
*** history ***
# v1: 2023-03-21
The first version which add allwinner-r40 support, supported features:
+ ccu
+ dram controller
+ uart
+ i2c and pmic(axp221)
+ sdcard
+ emac/gmac
Also provide a test case under avocado, running quickly test:
$ AVOCADO_ALLOW_LARGE_STORAGE=ye
From: qianfan Zhao
R40 has eight UARTs, support both 16450 and 16550 compatible modes.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 31 ---
include/hw/arm/allwinner-r40.h | 8
2 files changed, 36 insertions(+), 3 deletions(-)
diff --gi
From: qianfan Zhao
TWI(i2c) is designed to be used as an interface between CPU host and the
serial 2-Wire bus. It can support all standard 2-Wire transfer, can be
operated in standard mode(100kbit/s) or fast-mode, supporting data rate
up to 400kbit/s.
Signed-off-by: qianfan Zhao
---
hw/arm/all
From: qianfan Zhao
Only a few important registers are added, especially the SRAM_VER
register.
Signed-off-by: qianfan Zhao
---
hw/arm/Kconfig| 1 +
hw/arm/allwinner-r40.c| 7 +-
hw/misc/Kconfig | 3 +
hw/misc/allwinner-sramc.c | 1
From: qianfan Zhao
A64's sd register was similar to H3, and it introduced a new register
named SAMP_DL_REG location at 0x144. The dma descriptor buffer size of
mmc2 is only 8K and the other mmc controllers has 64K.
Signed-off-by: qianfan Zhao
---
hw/sd/allwinner-sdhost.c | 70 +
From: qianfan Zhao
The CCU provides the registers to program the PLLs and the controls
most of the clock generation, division, distribution, synchronization
and gating.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: qian
From: qianfan Zhao
R40 has two ethernet controllers named as emac and gmac. The emac is
compatibled with A10, and the GMAC is compatibled with H3.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 48 --
hw/arm/bananapi_m2u.c | 3 +++
in
From: qianfan Zhao
This patch adds minimal support for AXP-221 PMU and connect it to
bananapi M2U board.
Signed-off-by: qianfan Zhao
---
hw/arm/Kconfig| 1 +
hw/arm/bananapi_m2u.c | 5 ++
hw/misc/Kconfig | 4 +
hw/misc/axp221.c | 196 +++
From: qianfan Zhao
Add documents for Banana Pi M2U
Signed-off-by: qianfan Zhao
---
docs/system/arm/bananapi_m2u.rst | 138 +++
1 file changed, 138 insertions(+)
create mode 100644 docs/system/arm/bananapi_m2u.rst
diff --git a/docs/system/arm/bananapi_m2u.rst b/doc
From: qianfan Zhao
R40 has SAMP_DL_REG register and mmc2 controller has only 8K dma buffer.
Fix it's compatible string.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-
From: qianfan Zhao
TWI(i2c) is designed to be used as an interface between CPU host and the
serial 2-Wire bus. It can support all standard 2-Wire transfer, can be
operated in standard mode(100kbit/s) or fast-mode, supporting data rate
up to 400kbit/s.
Signed-off-by: qianfan Zhao
---
hw/arm/all
From: qianfan Zhao
Add test case for booting from initrd and sd card.
Signed-off-by: qianfan Zhao
---
tests/avocado/boot_linux_console.py | 173
1 file changed, 173 insertions(+)
diff --git a/tests/avocado/boot_linux_console.py
b/tests/avocado/boot_linux_console.
From: qianfan Zhao
The CCU provides the registers to program the PLLs and the controls
most of the clock generation, division, distribution, synchronization
and gating.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: qian
From: qianfan Zhao
A64's sd register was similar to H3, and it introduced a new register
named SAMP_DL_REG location at 0x144. The dma descriptor buffer size of
mmc2 is only 8K and the other mmc controllers has 64K.
Signed-off-by: qianfan Zhao
---
hw/sd/allwinner-sdhost.c | 70 +
From: qianfan Zhao
Types of memory that the SDRAM controller supports are DDR2/DDR3
and capacities of up to 2GiB. This commit adds emulation support
of the Allwinner R40 SDRAM controller.
This driver only support 256M, 512M and 1024M memory now.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinne
From: qianfan Zhao
Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
and a Mali400 MP2 GPU from ARM. It's also known as the Allwinner T3
for In-Car Entertainment usage, A40i and A40pro are variants that
differ in applicable temperatures range (industrial and military).
This patch
From: qianfan Zhao
*** history ***
# v1: 2023-03-21
The first version which add allwinner-r40 support, supported features:
+ ccu
+ dram controller
+ uart
+ i2c and pmic(axp221)
+ sdcard
+ emac/gmac
Also provide a test case under avocado, running quickly test:
$ AVOCADO_ALLOW_LARGE_STORAGE=ye
From: qianfan Zhao
R40 has eight UARTs, support both 16450 and 16550 compatible modes.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 32
include/hw/arm/allwinner-r40.h | 7 +++
2 files changed, 39 insertions(+)
diff --git a/hw/arm/allwi
From: qianfan Zhao
TWI(i2c) is designed to be used as an interface between CPU host and the
serial 2-Wire bus. It can support all standard 2-Wire transfer, can be
operated in standard mode(100kbit/s) or fast-mode, supporting data rate
up to 400kbit/s.
Signed-off-by: qianfan Zhao
---
hw/arm/all
From: qianfan Zhao
This patch adds minimal support for AXP-221 PMU and connect it to
bananapi M2U board.
Signed-off-by: qianfan Zhao
---
hw/arm/Kconfig| 1 +
hw/arm/bananapi_m2u.c | 5 ++
hw/misc/Kconfig | 4 +
hw/misc/axp221.c | 196 +++
From: qianfan Zhao
The CCU provides the registers to program the PLLs and the controls
most of the clock generation, division, distribution, synchronization
and gating.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: qian
From: qianfan Zhao
R40 has SAMP_DL_REG register and mmc2 controller has only 8K dma buffer.
Fix it's compatible string.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-
From: qianfan Zhao
R40 has two ethernet controllers named as emac and gmac. The emac is
compatibled with A10, and the GMAC is compatibled with H3.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 46 --
include/hw/arm/allwinner-r40.h | 6 +
From: qianfan Zhao
Types of memory that the SDRAM controller supports are DDR2/DDR3
and capacities of up to 2GiB. This commit adds emulation support
of the Allwinner R40 SDRAM controller.
This driver only support 256M, 512M and 1024M memory now.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinne
From: qianfan Zhao
v1: 2023-03-02
The first three patches try fix allwinner i2c driver and I already send them
as a standalone PR and can read it from:
https://patchwork.kernel.org/project/qemu-devel/patch/20230220081252.25348-3-qianfangui...@163.com/
Hope that patch can merged first before t
From: qianfan Zhao
TWI_CNTR_INT_FLAG is W1C(write 1 to clear and write 0 has non-effect)
register on SUN6i based SoCs, we should lower interrupt when the guest
set this bit.
The linux kernel will hang in irq handler(mv64xxx_i2c_intr) if no
device connected on the i2c bus, next is the trace log:
From: qianfan Zhao
A64's sd register was similar to H3, and it introduced a new register
named SAMP_DL_REG location at 0x144. The dma descriptor buffer size of
mmc2 is only 8K and the other mmc controllers has 64K.
Signed-off-by: qianfan Zhao
---
hw/sd/allwinner-sdhost.c | 70 +
From: qianfan Zhao
Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
and a Mali400 MP2 GPU from ARM. It's also known as the Allwinner T3
for In-Car Entertainment usage, A40i and A40pro are variants that
differ in applicable temperatures range (industrial and military).
This patch
From: qianfan Zhao
Next is an example when read/write trace enabled:
allwinner_i2c_write write XADDR(0x04): 0x00
allwinner_i2c_write write CNTR(0x0c): 0x50 M_STP BUS_EN
allwinner_i2c_write write CNTR(0x0c): 0xe4 A_ACK M_STA BUS_EN INT_EN
allwinner_i2c_read readCNTR(0x0c): 0xcc A_ACK IN
From: qianfan Zhao
Allwinner h3 has 4 twi(i2c) devices named twi0, twi1, twi2 and r_twi.
The registers are compatible with TYPE_AW_I2C_SUN6I, write 1 to clear
control register's INT_FLAG bit.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-h3.c | 29 +
incl
From: qianfan Zhao
R40 has eight UARTs, support both 16450 and 16550 compatible modes.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 32
include/hw/arm/allwinner-r40.h | 7 +++
2 files changed, 39 insertions(+)
diff --git a/hw/arm/allwi
From: qianfan Zhao
Allwinner h3 has 4 twi(i2c) devices named twi0, twi1, twi2 and r_twi.
The registers are compatible with TYPE_AW_I2C_SUN6I, write 1 to clear
control register's INT_FLAG bit.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-h3.c | 29 +
incl
From: qianfan Zhao
Next is an example when read/write trace enabled:
allwinner_i2c_write write XADDR(0x04): 0x00
allwinner_i2c_write write CNTR(0x0c): 0x50 M_STP BUS_EN
allwinner_i2c_write write CNTR(0x0c): 0xe4 A_ACK M_STA BUS_EN INT_EN
allwinner_i2c_read readCNTR(0x0c): 0xcc A_ACK IN
From: qianfan Zhao
TWI_CNTR_INT_FLAG is W1C(write 1 to clear and write 0 has non-effect)
register on SUN6i based SoCs, we should lower interrupt when the guest
set this bit.
The linux kernel will hang in irq handler(mv64xxx_i2c_intr) if no
device connected on the i2c bus, next is the trace log:
From: qianfan Zhao
Next is an example when allwinner_i2c_rw enabled:
allwinner_i2c_rw write CNTR[0x0c]: 50 { M_STP BUS_EN }
allwinner_i2c_rw write CNTR[0x0c]: e4 { A_ACK M_STA BUS_EN INT_EN }
allwinner_i2c_rw read CNTR[0x0c]: cc { A_ACK INT_FLAG BUS_EN INT_EN }
allwinner_i2c_rw read
From: qianfan Zhao
TWI_CNTR_INT_FLAG is W1C(write 1 to clear and write 0 has non-effect)
register, we should lower interrupt when the guest write this bit.
The linux kernel will hang in irq handler(mv64xxx_i2c_intr) if no
device connected on the i2c bus, next is the trace log:
[7.004130] ax
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