On 2/3/21 10:04 AM, Peter Maydell wrote:
On Wed, 3 Feb 2021 at 14:50, Michael Nawrocki
wrote:
On 2/2/21 6:29 AM, Peter Maydell wrote:
I see what you mean. Does QEMU support AArch64-only CPU models, and if
so, is there a way to determine if the CPU has AArch32?
We don't have any currently, bu
The FW and AW bits of SCR_EL3 are RES1 only in some contexts. Force them
to 1 only when there is no support for AArch32 at EL1 or above.
The reset value will be 0x30 only if the CPU is AArch64-only; if there
is support for AArch32 at EL1 or above, it will be reset to 0.
Also adds helper function
The SCR_EL3 register reset value (0) and the value produced when
writing 0 via the scr_write function (set as writefn in the register
struct) differ. This causes migration to fail.
Ultimately, this is due to incorrect handling of context-dependent
behavior of the RES1 bits of SCR_EL3. The FW and
On 2/2/21 6:29 AM, Peter Maydell wrote:
On Thu, 28 Jan 2021 at 14:31, Mike Nawrocki
wrote:
Fixes an issue in migration where the reset value of SCR and the value
produced by scr_write via the writefn for SCR_EL3 mismatch.
Signed-off-by: Mike Nawrocki
---
target/arm/helper.c | 2 +-
1 file
The SCR_EL3 register reset value (0) and the value produced when
writing 0 via the scr_write function (set as writefn in the register
struct) differ. This causes migration to fail.
I believe the solution is to specify a raw_writefn for that register.
Failing invocation:
$ qemu-system-arm -machin
Fixes an issue in migration where the reset value of SCR and the value
produced by scr_write via the writefn for SCR_EL3 mismatch.
Signed-off-by: Mike Nawrocki
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
in
