On 2024/11/8 下午9:55, Peter Maydell wrote:
In extioi_setirq() we try to operate on a bit array stored as an
array of uint32_t using the set_bit() and clear_bit() functions
by casting the pointer to 'unsigned long *'.
This has two problems:
* the alignment of 'uint32_t' is less than that of 'u
On 2024/11/7 下午7:28, Peter Maydell wrote:
On Thu, 31 Oct 2024 at 06:55, Bibo Mao wrote:
With generic cpu reset interface, pc register is entry of FLASH for
UEFI BIOS. However with direct kernel booting requirement, there is
little different, pc register of primary cpu is entry address of EL
On 2024/11/6 下午6:56, Igor Mammedov wrote:
On Wed, 30 Oct 2024 09:50:56 +0800
maobibo wrote:
Hi Zhao,
On 2024/10/29 下午9:37, Zhao Liu wrote:
(CC Igor since I want to refer his comment on hotplug design.)
Hi Bibo,
I have some comments about your hotplug design.
[snip]
+static void
On 2024/11/6 下午6:41, Igor Mammedov wrote:
On Tue, 29 Oct 2024 21:19:15 +0800
Zhao Liu wrote:
Hi Bibo,
[snip]
+In the CPU topology relationship, When we know the ``socket_id`` ``core_id``
+and ``thread_id`` of the CPU, we can calculate its ``arch_id``:
+
+``arch_id = (socket_id * S) + (co
On 2024/11/5 下午9:58, Igor Mammedov wrote:
On Mon, 4 Nov 2024 14:34:35 +0800
Bibo Mao wrote:
On virt machine, enable CPU hotplug feature has_hotpluggable_cpus. For
hot-added CPUs after power on, interrupt pin of extioi and ipi interrupt
controller need connect to pins of new CPU.
Also chan
It passed to compile on riscv machine, and the testbed is riscv qemu VM.
Regards
Bibo Mao
On 2024/10/30 下午12:06, Alistair Francis wrote:
On Wed, Oct 30, 2024 at 11:47 AM gaosong wrote:
在 2024/10/28 下午5:55, maobibo 写道:
On 2024/10/28 下午3:39, gaosong wrote:
在 2024/10/28 上午10:38, Bibo Mao 写
On 2024/10/29 下午9:48, Zhao Liu wrote:
[snip]
@@ -1382,8 +1384,40 @@ static void virt_cpu_pre_plug(HotplugHandler
*hotplug_dev,
}
if (cpu->phy_id == UNSET_PHY_ID) {
-error_setg(&local_err, "CPU hotplug not supported");
-goto out;
+if ((cpu->thread_id
Hi Zhao,
On 2024/10/29 下午9:37, Zhao Liu wrote:
(CC Igor since I want to refer his comment on hotplug design.)
Hi Bibo,
I have some comments about your hotplug design.
[snip]
+static void virt_cpu_pre_plug(HotplugHandler *hotplug_dev,
+ DeviceState *dev, Error
Hi Zhao,
Thanks for reviewing the patch.
On 2024/10/29 下午9:19, Zhao Liu wrote:
Hi Bibo,
[snip]
+In the CPU topology relationship, When we know the ``socket_id`` ``core_id``
+and ``thread_id`` of the CPU, we can calculate its ``arch_id``:
+
+``arch_id = (socket_id * S) + (core_id * C) + (thre
On 2024/10/28 下午3:39, gaosong wrote:
在 2024/10/28 上午10:38, Bibo Mao 写道:
since 6.11, unistd.h includes header file unistd_64.h directly on
some platforms, here add unistd_64.h on these platforms. Affected
platforms are ARM64, LoongArch64 and Riscv. Otherwise there will
be compiling error such
Reviewed-by: Bibo Mao
On 2024/10/28 上午9:57, Sia Jee Heng wrote:
Update the SPCR table to accommodate the SPCR Table revision 4 [1].
The SPCR table has been modified to adhere to the revision 4 format [2].
[1]:
https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-con
On 2024/8/29 上午9:59, Sia Jee Heng wrote:
Update the SPCR table to accommodate the SPCR Table revision 4 [1].
The SPCR table has been modified to adhere to the revision 4 format [2].
[1]:
https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
On 2024/10/23 上午9:22, maobibo wrote:
On 2024/10/23 上午2:54, Richard Henderson wrote:
On 10/22/24 05:42, Bibo Mao wrote:
For user tcg, there is no physical cpu id provided and logic cpuid
is used. For system emulation, physical cpu id is provided, initial
value of register CSR CPUID can be
On 2024/10/23 上午2:54, Richard Henderson wrote:
On 10/22/24 05:42, Bibo Mao wrote:
For user tcg, there is no physical cpu id provided and logic cpuid
is used. For system emulation, physical cpu id is provided, initial
value of register CSR CPUID can be set from physical cpu id.
Signed-off-by:
On 2024/10/16 下午4:41, gaosong wrote:
在 2024/10/16 下午4:13, maobibo 写道:
ping.
@Song
Could you give some comments since it is LoongArch specific?
Regards
Bibo Mao
On 2024/9/29 下午3:22, Bibo Mao wrote:
KVM LBT supports on LoongArch requires the linux-header kvm_para.h,
also unistd_64.h is
ping.
@Song
Could you give some comments since it is LoongArch specific?
Regards
Bibo Mao
On 2024/9/29 下午3:22, Bibo Mao wrote:
KVM LBT supports on LoongArch requires the linux-header kvm_para.h,
also unistd_64.h is required by unistd.h on LoongArch since 6.11
Signed-off-by: Bibo Mao
---
s
On 2024/10/15 下午10:31, Salil Mehta wrote:
HI Bibo,
From: maobibo
Sent: Tuesday, October 15, 2024 4:31 AM
To: Salil Mehta ; qemu-devel@nongnu.org;
qemu-...@nongnu.org; m...@redhat.com
With cpu-add/cpu-del command tested on LoongArch system, no migration
tested. There is no
With cpu-add/cpu-del command tested on LoongArch system, no migration
tested. There is no negative influence with LoongArch cpu hotplug.
Regards
Bibo Mao
On 2024/10/15 上午3:22, Salil Mehta via wrote:
Certain CPU architecture specifications [1][2][3] prohibit changes to the CPUs
*presence* after
Hi Salil,
On 2024/10/15 上午3:59, Salil Mehta wrote:
Hi Bibo,
From: maobibo
Sent: Monday, October 14, 2024 9:53 AM
To: qemu-devel@nongnu.org; Salil Mehta
Cc: Michael S. Tsirkin ; Peter Maydell
; Salil Mehta ;
zhukeqian ; Jonathan Cameron
; Gavin Shan ;
Vishnu Pajjuri
Hi Salil,
When I debug cpu hotplug on LoongArch system, It reports error like this:
ACPI BIOS Error (bug): Could not resolve symbol [\_SB.GED.CSCN],
AE_NOT_FOUND
ACPI Error: Aborting method \_SB.GED._EVT due to previous error
(AE_NOT_FOUND)
acpi-ged ACPI0013:00: IRQ method executio
On 2024/9/23 下午9:02, gaosong wrote:
在 2024/9/10 上午10:24, maobibo 写道:
On 2024/9/9 下午9:13, gaosong wrote:
在 2024/9/9 下午7:52, gaosong 写道:
在 2024/9/4 下午2:18, Bibo Mao 写道:
Six registers scr0 - scr3, eflags and ftop are added in percpu
vmstate.
And two functions kvm_loongarch_get_lbt
Hi Tiezhu,
Does mainline gdb support to dump LBT register now?
Regards
Bibo Mao
On 2024/9/23 下午9:02, gaosong wrote:
在 2024/9/10 上午10:24, maobibo 写道:
On 2024/9/9 下午9:13, gaosong wrote:
在 2024/9/9 下午7:52, gaosong 写道:
在 2024/9/4 下午2:18, Bibo Mao 写道:
Six registers scr0 - scr3, eflags and
On 2024/9/17 下午3:44, Igor Mammedov wrote:
On Sat, 14 Sep 2024 10:25:45 +0800
maobibo wrote:
On 2024/9/13 下午8:41, Igor Mammedov wrote:
On Wed, 11 Sep 2024 11:09:21 +0800
Bibo Mao wrote:
Macro definition is added for acpi sleep control register, so that
ged emulation driver can use
Hi Xianglai,
I do not find any usage about function kvm_irqchip_commit_routes() in
your patch-set, do I miss something?
Regards
Bibo Mao
On 2024/9/10 下午8:18, Xianglai Li wrote:
Added pch_msi interrupt controller handling
during kernel emulation of irq chip.
Signed-off-by: Xianglai Li
---
C
On 2024/9/14 上午10:58, Richard Henderson wrote:
On 9/13/24 18:43, Bibo Mao wrote:
Variable env->cf[i] is defined as bool type, it cannot be used with left
shifting operation.
Not true; it promotes to 'int'. But that isn't wide enough for the
value that you're trying to construct.
yeap, yo
On 2024/9/13 下午8:41, Igor Mammedov wrote:
On Wed, 11 Sep 2024 11:09:21 +0800
Bibo Mao wrote:
Macro definition is added for acpi sleep control register, so that
ged emulation driver can use this, also it can be used in FDT table if
ged is exposed with FDT table.
Signed-off-by: Bibo Mao
---
On 2024/9/14 上午1:19, Philippe Mathieu-Daudé wrote:
On 12/9/24 04:35, Bibo Mao wrote:
From: bibo mao
For header file hw/intc/loongarch_pch_pic.h, add common file
hw/intc/loongarch_pic_common.h and remove duplicated macro definition
in file loongarch_pch_pic.h
Signed-off-by: Bibo Mao
---
On 2024/9/13 下午4:02, Markus Armbruster wrote:
Thomas Huth writes:
On 08/05/2024 05.11, Bibo Mao wrote:
On LoongArch system, there is only virt machine type now, name
LOONGARCH_MACHINE is confused, rename it with LOONGARCH_VIRT_MACHINE.
Machine name about Other real hw boards can be added i
On 2024/9/10 下午8:18, Xianglai Li wrote:
Added pch_pic interrupt controller for kvm emulation.
The main process is to send the command word for
creating an pch_pic device to the kernel,
Delivers the pch pic interrupt controller configuration
register base address to the kernel.
When the VM is s
Song,
On 2024/9/12 下午7:35, gaosong wrote:
在 2024/9/11 上午11:09, Bibo Mao 写道:
ACPI ged is used for power management on LoongArch virt platform, in
general it is parsed from acpi table. However if system boot directly
from
elf kernel, no UEFI bios is provided and acpi table cannot be used also
On 2024/9/10 下午8:18, Xianglai Li wrote:
Added extioi interrupt controller for kvm emulation.
The main process is to send the command word for
creating an extioi device to the kernel.
When the VM is saved, the ioctl obtains the related
data of the extioi interrupt controller in the kernel
and s
On 2024/9/11 上午1:32, Michael S. Tsirkin wrote:
On Fri, Sep 06, 2024 at 10:19:42AM +0800, Bibo Mao wrote:
Macro definition is added for acpi ged sleep register, so that ged
emulation driver can use this, also it can be used in FDT table if
ged is exposed with FDT table.
Signed-off-by: Bibo Ma
On 2024/9/9 下午9:13, gaosong wrote:
在 2024/9/9 下午7:52, gaosong 写道:
在 2024/9/4 下午2:18, Bibo Mao 写道:
Six registers scr0 - scr3, eflags and ftop are added in percpu vmstate.
And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are added
to save/restore lbt registers.
Signed-off-by: B
On 2024/9/7 下午10:34, Jason A. Donenfeld wrote:
In order to support additional channels of communication using
`-serial`, add several serial ports, up to the standard 4 generally
supported by the 8250 driver.
Signed-off-by: Jason A. Donenfeld
---
hw/loongarch/acpi-build.c | 23
te:
In order to support additional channels of communication using
`-serial`, add several serial ports, up to the standard 4 generally
supported by the 8250 driver.
Signed-off-by: Jason A. Donenfeld
---
As I don't use ACPI, I haven't tested the ACPI part of this, which
Maobibo wrote.
hw/lo
Add huacai who is maintainer of Loongarch Linux kernel.
On 2024/9/6 下午10:55, Jason A. Donenfeld wrote:
Hi,
It appears that as of QEMU 9.1, it's possible to boot LoongArch machines
that don't provide EFI or ACPI.
Would you consider removing the `select ACPI` and `select EFI` from the
arch Kconf
On 2024/9/6 下午12:49, Jason A. Donenfeld wrote:
In order to support additional channels of communication using
`-serial`, add several serial ports, up to the standard 4 generally
supported by the 8250 driver.
Signed-off-by: Jason A. Donenfeld
---
hw/loongarch/virt.c| 24
:55+, Jason A. Donenfeld wrote:
On Thu, Sep 05, 2024 at 07:25:05AM +0200, Thomas Weißschuh wrote:
On 2024-09-05 06:04:12+, Jason A. Donenfeld wrote:
On Thu, Sep 5, 2024 at 5:45 AM maobibo wrote:
Jason,
With the latest qemu 9.1 version, elf format booting is supported.
Thanks, I just
On 2024/9/5 下午11:49, Jason A. Donenfeld wrote:
On Thu, Sep 05, 2024 at 04:54:41PM +0200, Jason A. Donenfeld wrote:
On Thu, Sep 05, 2024 at 02:11:32PM +0800, maobibo wrote:
On 2024/9/5 下午1:25, Thomas Weißschuh wrote:
On 2024-09-05 06:04:12+, Jason A. Donenfeld wrote:
On Thu, Sep 5
On 2024/9/5 下午1:25, Thomas Weißschuh wrote:
On 2024-09-05 06:04:12+, Jason A. Donenfeld wrote:
On Thu, Sep 5, 2024 at 5:45 AM maobibo wrote:
Jason,
With the latest qemu 9.1 version, elf format booting is supported.
Thanks, I just figured this out too, about 4 minutes ago. Excellent
/linux_larch/vmlinux -initrd ramdisk -append "root=/dev/ram
rdinit=/sbin/init console=ttyS0,115200" --nographic
Regards
Bibo Mao
On 2024/9/5 上午11:12, Jason A. Donenfeld wrote:
On Tue, Oct 10, 2023 at 09:12:46AM +0800, maobibo wrote:
Thomas,
Thanks for reporting this issue.
It is the probl
On 2024/8/21 上午2:42, Jiaxun Yang wrote:
The size of lowram should be "gap" instead of the whole node.
This is failing kernel's sanity check:
[0.00] ACPI: SRAT: Node 0 PXM 0 [mem 0x-0x]
[0.00] ACPI: SRAT: Node 0 PXM 0 [mem 0x8000-0x16fff]
[0.00]
Philippe,
I checkout the latest code, it works well.
Thanks for your efforts.
Regards
Bibo Mao
On 2024/8/6 下午8:51, Philippe Mathieu-Daudé wrote:
From: Bibo Mao
We'll have to add LoongsonIPIClass in few commits,
so rename LoongsonIPI as LoongsonIPIState for clarity.
Signed-off-by: Bibo Mao
Reviewed-by: Bibo Mao
On 2024/7/18 下午4:32, Song Gao wrote:
Remove extioi INT_encode encode mode, because we don't emulate it.
Signed-off-by: Song Gao
---
include/hw/intc/loongarch_extioi.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/hw/intc/loongarch_extioi.h
b/include/hw/i
On 2024/7/18 下午3:25, Song Gao wrote:
Remove extioi INT_encode encode mode, because we don't emulate it.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c| 6 --
include/hw/intc/loongarch_extioi.h | 1 -
2 files changed, 7 deletions(-)
diff --git a/hw/loongarch/virt.c b
On 2024/7/18 上午5:46, Philippe Mathieu-Daudé wrote:
From: Bibo Mao
In preparation to extract common IPI code in few commits,
extract loongson_ipi_common_realize().
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Signed-off-by: Philippe Mathieu-Daudé
--
On 2024/7/16 下午2:40, Philippe Mathieu-Daudé wrote:
On 16/7/24 03:29, maobibo wrote:
On 2024/7/16 上午9:04, maobibo wrote:
On 2024/7/15 下午11:17, Philippe Mathieu-Daudé wrote:
On 4/7/24 05:37, Bibo Mao wrote:
Now loongson ipi and loongarch ipi share the same code with different
macro
On 2024/7/11 上午10:44, Song Gao wrote:
GDB already support LoongArch vector extension[1], QEMU gdb adds
LoongArch vector registers support, so that users can use 'info all-registers'
to get all vector registers values.
[1]:
https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=1e9569f
On 2024/7/16 上午9:04, maobibo wrote:
On 2024/7/15 下午11:17, Philippe Mathieu-Daudé wrote:
On 4/7/24 05:37, Bibo Mao wrote:
Now loongson ipi and loongarch ipi share the same code with different
macro, loongson ipi has its separate function such mmio region,
loongarch ipi has other
On 2024/7/15 下午11:31, Philippe Mathieu-Daudé wrote:
On 4/7/24 05:37, Bibo Mao wrote:
Loongson ipi common class and instance is created here, it comes
from file loongson_ipi mostly. For the new added loongson ipi
common class, there is four interfaces defined here:
1. Interfaces pre_save/pos
On 2024/7/15 下午11:17, Philippe Mathieu-Daudé wrote:
On 4/7/24 05:37, Bibo Mao wrote:
Now loongson ipi and loongarch ipi share the same code with different
macro, loongson ipi has its separate function such mmio region,
loongarch ipi has other requirement such as irqchip in kernel.
Interrupt
On 2024/7/15 下午5:57, Philippe Mathieu-Daudé wrote:
On 27/6/24 14:58, Philippe Mathieu-Daudé wrote:
v2:
- Only skip mmio-related code in loongson_ipi_realize()
Jiaxun Yang (1):
hw/intc/loongson_ipi: Gate MMIO regions creation with property
include/hw/intc/loongson_ipi.h | 1 +
hw/intc
On 2024/6/21 下午2:54, Song Gao wrote:
GDB already support LoongArch vector extension[1], QEMU gdb adds
LoongArch vector registers support, so that users can use 'info all-registers'
to get all vector registers values.
[1]:
https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=1e9569f3
On 2024/7/10 下午12:00, Jiaxun Yang wrote:
在2024年7月9日七月 下午8:04，maobibo写道：
Hi Philippe/Jiaxun,
Could you do me a favor giving a review about this patch?
Hi Bibo,
I’m currently traveling, will test and review next week.
I’m not really convinced to give a R-b but I’m fine with a T-b.
That
Hi Philippe/Jiaxun,
Could you do me a favor giving a review about this patch?
Regards
Bibo Mao
On 2024/7/4 上午11:37, Bibo Mao wrote:
Now loongson ipi and loongarch ipi share the same code with different
macro, loongson ipi has its separate function such mmio region,
loongarch ipi has other requ
On 2024/7/5 上午10:18, Song Gao wrote:
We set the value of register CSR_PRCFG3, but left out CSR_PRCFG1
and CSR_PRCFG2. Set CSR_PRCFG1 and CSR_PRCFG2 according to the
default values of the physical machine.
Signed-off-by: Song Gao
---
v2:
- Add a new patch fix set CSR_CRMD wrong value;
- S
On 2024/7/5 上午10:18, Song Gao wrote:
After cpu_reset, DATF in CSR_CRMD is 0, DATM is 0.
See the manual[1] 6.4.
[1]:
https://github.com/loongson/LoongArch-Documentation/releases/download/2023.04.20/LoongArch-Vol1-v1.10-EN.pdf
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 6 +++--
On 2024/7/4 下午7:12, Song Gao wrote:
We set the value of register CSR_PRCFG3, but left out CSR_PRCFG1
and CSR_PRCFG2. Set CSR_PRCFG1 and CSR_PRCFG2 according to the
default values of the physical machine.
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 6 ++
1 file changed, 6 inse
On 2024/7/3 下午5:43, Huacai Chen wrote:
On Wed, Jul 3, 2024 at 3:51 PM Jiaxun Yang wrote:
在2024年7月1日七月 下午2:57，Jiaxun Yang写道：
在2024年5月30日五月 上午7:49，Bibo Mao写道：
Loongson Binary Translation (LBT) is used to accelerate binary
translation, which contains 4 scratch registers (scr0 to scr3), x86
On 2024/7/3 下午3:33, Jiaxun Yang wrote:
在2024年7月3日七月 下午2:40，maobibo写道：
[...]
Hi Bobo,
MMIO is loongson ipi specific, it is not necessary to put into common
function. Functions loongson_ipi_core_readl/loongson_ipi_core_writel can
be exported in header file include/hw/intc
On 2024/7/3 下午2:16, Jiaxun Yang wrote:
在2024年7月3日七月 上午10:12，Bibo Mao写道：
Loongson ipi common class and instance is created here, it comes
from file loongson_ipi mostly. For the new added loongson ipi
common class, there is four interfaces defined here:
1. Interfaces pre_save/post_load are
On 2024/7/1 下午4:42, Jiaxun Yang wrote:
在2024年7月1日七月 上午8:32，maobibo写道：
[...]
+static void loongarch_cpu_check_lbt(CPUState *cs, Error **errp)
+{
+CPULoongArchState *env = cpu_env(cs);
+LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+bool kvm_supported;
+
+kvm_supported
On 2024/7/1 下午4:29, Jiaxun Yang wrote:
在2024年7月1日七月 上午8:22，maobibo写道：
On 2024/7/1 下午3:01, Jiaxun Yang wrote:
在2024年7月1日七月 上午7:44，maobibo写道：
Also this patch is problematic on LoongArch.
The original patch is to search physical cpuid rather than logic cpuid.
We want to make ipi module
On 2024/7/1 下午2:57, Jiaxun Yang wrote:
在2024年5月30日五月 上午7:49，Bibo Mao写道：
Loongson Binary Translation (LBT) is used to accelerate binary
translation, which contains 4 scratch registers (scr0 to scr3), x86/ARM
eflags (eflags) and x87 fpu stack pointer (ftop).
Now LBT feature is added in kvm m
On 2024/7/1 下午3:08, Jiaxun Yang wrote:
在2024年7月1日七月 上午2:35，maobibo写道：
[...]
How about split loongson_ipi.c into
loongson_ipi_base.c/loongson_ipi_loongson.c/loongson_ipi_loongarch.c,
File loongson_ipi_base.c contains the common code, loongson_ipi_xxx.c
contains arch specific. Soon we will
On 2024/7/1 下午3:01, Jiaxun Yang wrote:
在2024年7月1日七月 上午7:44，maobibo写道：
Also this patch is problematic on LoongArch.
The original patch is to search physical cpuid rather than logic cpuid.
We want to make ipi module better and better, however now it comes back
to initial state at the
com>
Signed-off-by: Philippe Mathieu-Daudé
Regards
Bibo Mao
On 2024/7/1 上午9:35, maobibo wrote:
Hi Philippe,
On 2024/6/27 下午9:02, Philippe Mathieu-Daudé wrote:
On 27/6/24 04:44, gaosong wrote:
在 2024/6/26 下午8:10, Philippe Mathieu-Daudé 写道:
Hi Bibo,
On 26/6/24 06:11, maobibo wrote:
Hi Philippe,
On 2024/6/27 下午9:02, Philippe Mathieu-Daudé wrote:
On 27/6/24 04:44, gaosong wrote:
在 2024/6/26 下午8:10, Philippe Mathieu-Daudé 写道:
Hi Bibo,
On 26/6/24 06:11, maobibo wrote:
On 2024/6/5 上午10:15, Jiaxun Yang wrote:
It was missed out in previous commit.
Fixes: b4a12dfc2132
On 2024/6/26 下午3:40, Jiaxun Yang wrote:
在2024年6月26日六月 上午5:11，maobibo写道：
[...]
It is different with existing implementation.
What do you mean? Isn't this the actual hardware behaviour?
With hw/intc/loongson_ipi.c, every vcpu has one ipi_mmio_mem, however on
loongarch ipi machine,
On 2024/6/5 上午10:15, Jiaxun Yang wrote:
It was missed out in previous commit.
Fixes: b4a12dfc2132 ("hw/intc/loongarch_ipi: Rename as loongson_ipi")
Signed-off-by: Jiaxun Yang
---
hw/intc/loongarch_ipi.c | 347
1 file changed, 347 deletions(
On 2024/6/14 下午10:03, Daniel P. Berrangé wrote:
On Fri, Jun 14, 2024 at 01:17:39PM +0800, maobibo wrote:
On 2024/6/14 下午12:27, Jiaxun Yang wrote:
在2024年6月14日六月 上午4:32，maobibo写道：
It is interesting.
How to wakeup VM if it sleeps in S3/S4, from emulated keyboard or
ethernet magic packet
On 2024/6/14 下午12:27, Jiaxun Yang wrote:
在2024年6月14日六月 上午4:32，maobibo写道：
It is interesting.
How to wakeup VM if it sleeps in S3/S4, from emulated keyboard or
ethernet magic packet or qemu monitor command in background?
Hi Bibo,
The best way to wake the guest is system_wakeup command in
It is interesting.
How to wakeup VM if it sleeps in S3/S4, from emulated keyboard or
ethernet magic packet or qemu monitor command in background?
Regards
Bibo Mao
On 2024/6/14 上午1:30, Jiaxun Yang wrote:
Hi all,
This series implemented S3 and S4 sleep for loongarch virt machine
and microv
On 2024/6/7 下午10:31, Peter Maydell wrote:
On Thu, 23 May 2024 at 02:48, Song Gao wrote:
From: Bibo Mao
Memory map table for fwcfg is used for UEFI BIOS, UEFI BIOS uses the first
entry from fwcfg memory map as the first memory HOB, the second memory HOB
will be used if the first memory HOB
On 2024/6/7 上午8:24, Richard Henderson wrote:
Use inline assembly because no release compiler allows
per-function selection of the ISA.
Signed-off-by: Richard Henderson
---
.../loongarch64/host/bufferiszero.c.inc | 143 ++
1 file changed, 143 insertions(+)
create mo
On 2024/6/6 上午11:42, Richard Henderson wrote:
On 6/5/24 20:36, maobibo wrote:
static biz_accel_fn const accel_table[] = {
buffer_is_zero_int_ge256,
#ifdef __loongarch_sx
buffer_is_zero_lsx,
#endif
#ifdef __loongarch_asx
buffer_is_zero_lasx,
#endif
};
static unsigned
On 2024/6/6 上午11:27, Richard Henderson wrote:
On 6/5/24 20:18, Richard Henderson wrote:
On 6/5/24 19:30, maobibo wrote:
On 2024/6/6 上午7:51, Richard Henderson wrote:
On 6/5/24 02:32, Bibo Mao wrote:
Different gcc versions have different features, macro CONFIG_LSX_OPT
and CONFIG_LASX_OPT
On 2024/6/6 上午7:51, Richard Henderson wrote:
On 6/5/24 02:32, Bibo Mao wrote:
Different gcc versions have different features, macro CONFIG_LSX_OPT
and CONFIG_LASX_OPT is added here to detect whether gcc supports
built-in lsx/lasx macro.
Function buffer_zero_lsx() is added for 128bit simd fpu
On 2024/6/5 下午7:53, Philippe Mathieu-Daudé wrote:
On 5/6/24 11:32, Bibo Mao wrote:
Lasx is 256bit vector FPU capability, lsx is 128bit vector VFP. lsx
is added already, lasx is added here.
Signed-off-by: Bibo Mao
---
host/include/loongarch64/host/cpuinfo.h | 1 +
util/cpuinfo-loongarch.c
On 2024/5/28 下午4:38, Song Gao wrote:
This patch adds a new board attribute 'v-eiointc'.
A value of true enables the virt extended I/O interrupt controller.
VMs working in kvm mode have 'v-eiointc' enabled by default.
Signed-off-by: Song Gao
---
include/hw/loongarch/virt.h | 1 +
target/l
On 2024/5/28 下午4:38, Song Gao wrote:
Use MemTxAttrs interface read_with_attrs/write_with_attrs
for virt_iocsr_misc_ops.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 36
1 file changed, 24 insertions(+), 12 deletions(-)
diff --git a/hw/loongarch/v
On 2024/5/28 下午8:56, gaosong wrote:
在 2024/5/28 上午9:07, maobibo 写道:
Hi Philippe,
Thanks for reviewing my patch.
I reply inline.
On 2024/5/27 下午6:37, Philippe Mathieu-Daudé wrote:
Hi Bibo,
On 27/5/24 10:35, Bibo Mao wrote:
Loongson Binary Translation (LBT) is used to accelerate binary
Thomas,
Thanks for reviewing the patch.
On 2024/5/29 下午3:10, Thomas Huth wrote:
On 28/05/2024 10.20, Bibo Mao wrote:
Add loongarch virt machine to the graph. It is a modified copy of
the existing riscv virtmachine in riscv-virt-machine.c
It contains a generic-pcihost controller, and an extra
On 2024/5/27 下午6:39, Philippe Mathieu-Daudé wrote:
Hi Bibo,
On 27/5/24 10:34, Bibo Mao wrote:
Loongson Binary Translation (LBT) is used to accelerate binary
translation. LBT feature is added in kvm mode, not supported in TCG
mode since it is not emulated. And only LBT feature is added here,
Hi Philippe,
Thanks for reviewing my patch.
I reply inline.
On 2024/5/27 下午6:37, Philippe Mathieu-Daudé wrote:
Hi Bibo,
On 27/5/24 10:35, Bibo Mao wrote:
Loongson Binary Translation (LBT) is used to accelerate binary
translation, which contains 4 scratch registers (scr0 to scr3), x86/ARM
efla
Song will online next week.
Please correct me if there is something wrong, song.
On 2024/5/24 上午7:50, Jiaxun Yang wrote:
在2024年5月21日五月 下午1:32，Song Gao写道：
On LoongArch, IRQs can be routed to four vcpus with hardware extioi.
This patch adds the extioi virt extension support so that the IRQ ca
On 2024/5/21 下午8:32, Song Gao wrote:
Use MemTxAttrs interface read_with_attrs/write_with_attrs
for virt_iocsr_misc_ops.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw
On 2024/5/21 下午8:32, Song Gao wrote:
On LoongArch, IRQs can be routed to four vcpus with hardware extioi.
This patch adds the extioi virt extension definition so that the IRQ can
route to 256 vcpus.
Signed-off-by: Song Gao
---
include/hw/intc/loongarch_extioi.h | 21 +++
hw/intc/loonga
On 2024/5/14 下午5:07, Song Gao wrote:
This patch adds a new board attribute 'v-eiointc'.
A value of true enables the virt extended I/O interrupt controller.
VMs working in kvm mode have 'v-eiointc' enabled by default.
Signed-off-by: Song Gao
---
include/hw/loongarch/virt.h | 2 +
target/
On 2024/5/14 下午5:07, Song Gao wrote:
On LoongArch, IRQs can be routed to four vcpus with hardware extioi.
This patch adds the extioi virt extension definition so that the IRQ can
route to 256 vcpus.
Signed-off-by: Song Gao
---
include/hw/intc/loongarch_extioi.h | 21 +++
hw/intc/loong
On 2024/5/15 下午5:01, gaosong wrote:
在 2024/5/14 下午7:51, Bibo Mao 写道:
Add loongarch virt machine to the graph. It is a modified copy of
the existing riscv virtmachine in riscv-virt-machine.c
It contains a generic-pcihost controller, and an extra function
loongarch_config_qpci_bus() to configu
Reviewed-by: Bibo Mao
On 2024/5/14 下午7:07, Song Gao wrote:
On kvm side, get_fpu/set_fpu save the vreg registers high 192bits,
but QEMU missing.
Signed-off-by: Song Gao
---
target/loongarch/kvm/kvm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/loongarch/kvm/kvm.c b/targ
On 2024/5/14 下午5:46, Song Gao wrote:
This patch adds PMU support, We just sets some cpucfg6 default value
to PMU config on kvm mode, and then check the PMU config with kvm ioctl
KVM_GET_DEVICE_ATTR.
e.g
'... -cpu max,pmu=on,pmnum=[1-16]';
'... -cpu max,pmu=on' (default pmnum = 4
On 2024/5/8 下午5:00, Thomas Huth wrote:
On 08/05/2024 10.55, Bibo Mao wrote:
Add boot-serial-test test case support on LoongArch system.
... and also the filter tests?
yes, it is :) Will update changelog in next version.
Signed-off-by: Bibo Mao
---
tests/qtest/boot-serial-test.c | 10
On 2024/5/7 下午2:10, Thomas Huth wrote:
On 07/05/2024 03.18, maobibo wrote:
On 2024/5/6 下午2:09, maobibo wrote:
On 2024/5/6 下午12:24, Thomas Huth wrote:
On 06/05/2024 05.02, Bibo Mao wrote:
On LoongArch system, there is only virt machine type now, name
LOONGARCH_MACHINE is confused
On 2024/5/6 下午2:09, maobibo wrote:
On 2024/5/6 下午12:24, Thomas Huth wrote:
On 06/05/2024 05.02, Bibo Mao wrote:
On LoongArch system, there is only virt machine type now, name
LOONGARCH_MACHINE is confused, rename it with VIRT_MACHINE. Machine name
about Other real hw boards can be added
On 2024/5/6 下午12:24, Thomas Huth wrote:
On 06/05/2024 05.02, Bibo Mao wrote:
On LoongArch system, there is only virt machine type now, name
LOONGARCH_MACHINE is confused, rename it with VIRT_MACHINE. Machine name
about Other real hw boards can be added in future.
Signed-off-by: Bibo Mao
---
Sure, I will rebase and send the new version.
Regards
Bibo Mao
On 2024/4/30 下午4:15, gaosong wrote:
Hi,
在 2024/3/18 下午4:01, Bibo Mao 写道:
One LoongArch virt machine platform, there is limitation for memory
map information. The minimum memory size is 256M and minimum memory
size for numa node0 i
On 2024/4/26 下午5:15, Song Gao wrote:
Message test is also missing there :(
Signed-off-by: Song Gao
Message-Id: <20240307164835.300412-7-gaos...@loongson.cn>
---
include/hw/loongarch/boot.h | 27 +
include/hw/loongarch/virt.h | 10 ++
hw/loongarch/boot.c
On 2024/4/26 下午5:15, Song Gao wrote:
Message text is missing here :(
Signed-off-by: Song Gao
Message-Id: <20240307164835.300412-4-gaos...@loongson.cn>
It is strange that there is "Message-Id:" string. Is it required here?
The others look good to me, especially when bootrom for AP is put a
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