Re: [PATCH] target/i386: do not expose ARCH_CAPABILITIES on AMD CPU

> Reported-by: Alexandre Chartre > Suggested-by: Daniel P. Berrangé > Signed-off-by: Paolo Bonzini > --- > target/i386/kvm/kvm.c | 6 +- > 1 file changed, 5 insertions(+), 1 deletion(-) Good to see this fix. Late but, Reviewed-by: Zhao Liu

Re: [PATCH v11 2/3] vfio: Move the TYPE_* to hw/vfio/types.h

| 10 +- > hw/vfio/types.h | 21 + > 2 files changed, 22 insertions(+), 9 deletions(-) > create mode 100644 hw/vfio/types.h Reviewed-by: Zhao Liu

Re: [PATCH-for-10.1] system/runstate: Document qemu_add_vm_change_state_handler_prio* in hdr

2 files changed, 30 insertions(+), 30 deletions(-) Reviewed-by: Zhao Liu

Re: [PATCH] i386/cpu: Cleanup host_cpu_max_instance_init()

get/i386/host-cpu.h | 1 - > 1 file changed, 1 deletion(-) Reviewed-by: Zhao Liu

Re: [PATCH v2 4/7] i386/cpu: Fix number of addressable IDs field for CPUID.01H.EBX[23:16]

> This makes sense. > > In this case though, the next patch, a62fef5829956 "i386/cpu: Fix cpu > number overflow in CPUID.01H.EBX[23:16]", becomes a one-liner: > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 2c9517f56d..5e55dd9ee5 100644 > --- a/target/i386/cpu.c > +++ b/target/i386

Re: [PATCH v2 4/7] i386/cpu: Fix number of addressable IDs field for CPUID.01H.EBX[23:16]

> Hi! > > Previous incarnation of this patch were Cc'd qemu-stable@, as it were > supposed to be picked up for the stable qemu series. However, this > incarnation is not Cc'd to stable, and, most importantly, it relies > on a feature which was introduced after all released qemu versions. > Namely

[PATCH for v10.1] i386/cpu: Move x86_ext_save_areas[] initialization to .instance_init

to .instance_init") Reported-by: Paolo Abeni Tested-by: Paolo Abeni Signed-off-by: Zhao Liu --- target/i386/cpu.c | 22 +++--- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index da7d8dca633e..251d5760a0bd 100644 --- a/

Re: boot failure on top of current git

On Wed, Jul 16, 2025 at 05:22:46PM +0200, Paolo Bonzini wrote: > Date: Wed, 16 Jul 2025 17:22:46 +0200 > From: Paolo Bonzini > Subject: Re: boot failure on top of current git > > On 7/16/25 16:44, Paolo Abeni wrote: > > Hi, > > > > I'm observing boot failure for a rhel-9.7 VM. I'm using qemu git

Re: [PATCH v2] intel_iommu: Allow both Status Write and Interrupt Flag in QI wait

On 2025/7/16 12:05, Konstantin Belousov wrote: On Wed, Jul 16, 2025 at 12:01:44PM +0800, Yi Liu wrote: On 2025/7/15 20:27, CLEMENT MATHIEU--DRIF wrote: On 15/07/2025 10:27 am, David Woodhouse wrote: On Tue, 2025-07-15 at 06:11 +, CLEMENT MATHIEU--DRIF wrote: On 14/07/2025 11:22 pm

Re: [PATCH v2 2/2] target/i386: Add TSA feature flag verw-clear

r". > > v1: > https://lore.kernel.org/qemu-devel/20250709104956.GAaG5JVO-74EF96hHO@fat_crate.local/ > --- > target/i386/cpu.c | 2 +- > target/i386/cpu.h | 2 ++ > 2 files changed, 3 insertions(+), 1 deletion(-) Reviewed-by: Zhao Liu

Re: [PATCH v2 1/2] target/i386: Add TSA attack variants TSA-SQ and TSA-L1

> https://lore.kernel.org/qemu-devel/20250709104956.GAaG5JVO-74EF96hHO@fat_crate.local/ > --- > target/i386/cpu.c | 17 + > target/i386/cpu.h | 6 ++ > 2 files changed, 23 insertions(+) Reviewed-by: Zhao Liu

Re: [PATCH v2] intel_iommu: Allow both Status Write and Interrupt Flag in QI wait

2025 15:28:09 GMT+01:00, Yi Liu wrote: Hi David, On 2025/7/14 16:00, David Woodhouse wrote: From: David Woodhouse I think this "if branch" can be moved just after the inv_desc non-zero reserved bit checking. Hence you don't need a ret at all. :) We want to return false if t

Re: [PATCH v2] intel_iommu: Allow both Status Write and Interrupt Flag in QI wait

Woodhouse wrote: On 14 July 2025 15:28:09 GMT+01:00, Yi Liu wrote: Hi David, On 2025/7/14 16:00, David Woodhouse wrote: From: David Woodhouse FreeBSD does both, and this appears to be perfectly valid. The VT-d spec even talks about the ordering (the status write should be done first

Re: [PATCH v2 7/7] i386/cpu: Honor maximum value for CPUID.8000001DH.EAX[25:14]

On Mon, Jul 14, 2025 at 09:51:25AM -0500, Moger, Babu wrote: > Date: Mon, 14 Jul 2025 09:51:25 -0500 > From: "Moger, Babu" > Subject: Re: [PATCH v2 7/7] i386/cpu: Honor maximum value for > CPUID.801DH.EAX[25:14] > > Hi Zhao, > > On 7/14/25 03:08, Zhao Liu

Re: [PATCH v2] intel_iommu: Allow both Status Write and Interrupt Flag in QI wait

inv_desc->lo); return false; } I think this "if branch" can be moved just after the inv_desc non-zero reserved bit checking. Hence you don't need a ret at all. :) btw. I'm also asking if VT-d spec allows it or not. So let's wait for a while.. -return true; +return ret; } static bool vtd_process_context_cache_desc(IntelIOMMUState *s, -- Regards, Yi Liu

[PATCH] gtk: Skip drawing if console surface is NULL

laceholder surface to the console when there is nothing to display. Resolves: Coverity CID 1610328 Signed-off-by: Weifeng Liu --- ui/gtk-egl.c | 5 + ui/gtk-gl-area.c | 5 + 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/ui/gtk-egl.c b/ui/gtk-egl.c index 0b787bea25..

Re: [PATCH v2 2/7] i386/cpu: Mark CPUID 0x80000008 ECX bits[0:7] & [12:15] as reserved for Intel/Zhaoxin

> > if (threads_per_pkg > 1) { > > /* > > - * Bits 15:12 is "The number of bits in the initial > > - * Core::X86::Apic::ApicId[ApicId] value that indicate > > - * thread ID within a package". > > - * Bits 7:0 is "The number of

[PATCH v2 1/7] i386/cpu: Mark EBX/ECX/EDX in CPUID 0x80000000 leaf as reserved for Intel

Tested-by: Yi Lai Signed-off-by: Zhao Liu --- Changes Since v1: * Consider Zhaoxin CPU. (Ewan) --- target/i386/cpu.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 8d67cadec2f2..37e4bf51d890 100644 --- a/target/i386/cpu.c

[PATCH v2 0/7] i386/cpu: Clean Up Reserved CPUID Leaves & Topology Overflow Fix

erflow in CPUID.01H.EBX[23:16] i386/cpu: Fix overflow of cache topology fields in CPUID.04H Zhao Liu (4): i386/cpu: Mark EBX/ECX/EDX in CPUID 0x8000 leaf as reserved for Intel i386/cpu: Mark CPUID 0x8008 ECX bits[0:7] & [12:15] as reserved for Intel/Zhaoxin i386/cpu: Reor

[PATCH v2 4/7] i386/cpu: Fix number of addressable IDs field for CPUID.01H.EBX[23:16]

Logical processor count". Current result meets our expectation. So round up CPUID.01H.EBX[23:16] to the nearest power-of-2 integer only for Intel platform to solve the unexpected result. Use the "x-vendor-cpuid-only-v2" compat option to fix this issue. Reviewed-by: Zhao Liu Signed-off-b

[PATCH v2 5/7] i386/cpu: Fix cpu number overflow in CPUID.01H.EBX[23:16]

lue written to EBX[23:16] to 255 as the HW does. Cc: qemu-sta...@nongnu.org Reviewed-by: Xiaoyao Li Signed-off-by: Qian Wen Signed-off-by: Zhao Liu --- Changes Since New v1 [**]: * Rebase. Changes Since Original v4 [*]: * Rebase on addressable ID fixup. * Drop R/b tags since the code base chan

[PATCH v2 3/7] i386/cpu: Reorder CPUID leaves in cpu_x86_cpuid()

Sort the CPUID leaves strictly by index to facilitate checking and changing. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 60 +++ 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index

[PATCH v2 2/7] i386/cpu: Mark CPUID 0x80000008 ECX bits[0:7] & [12:15] as reserved for Intel/Zhaoxin

to describe CPU topology, which includes similar information, Intel and Zhaoxin will not implement ECX bits[0:7] and bits[12:15] of 0x8008. Therefore, mark these two fields as reserved and clear them for Intel and Zhaoxin guests. Reviewed-by: Tao Su Tested-by: Yi Lai Signed-off-by: Zhao Liu

[PATCH v2 6/7] i386/cpu: Fix overflow of cache topology fields in CPUID.04H

Signed-off-by: Zhao Liu --- Changes Since New v1 [**]: * Provide an overflow example of EAX[14:25]. Changes Since Original v4 [*]: * Rebase on addressable ID fixup. * Drop R/b tags since the code base changes. * Teak bits 25-14 as well and add the comment. * Fix overflow for host-cache-info

[PATCH v2 7/7] i386/cpu: Honor maximum value for CPUID.8000001DH.EAX[25:14]

ned-off-by: Zhao Liu --- Changes Since RFC v1 [*]: * Correct the RFC's description, now there's the overflow case. Provide an overflow example. RFC: * Although there are currently no overflow cases, to avoid any potential issue, add the overflow check, just as I did for

Re: [PATCH for v10.0.0] target/riscv/kvm/kvm-cpu: Fixed the issue of resume after QEMU+KVM migration

Hi XieBo, Could you give the method on how to test it? Thanks, Zhiwei 获取Outlook for Android From: qemu-devel-bounces+baxiantai=gmail@nongnu.org on behalf of 谢波 Sent: Friday, July 11, 2025 5:28:10 PM To: qemu-devel@nongnu.org Cc: al

[PATCH v2 9/9] i386/cpu: Enable 0x1f leaf for YongFeng by default

Host YongFeng CPU has 0x1f leaf by default, so that enable it for Guest CPU by default as well. Suggested-by: Ewan Hai Tested-by: Yi Lai Signed-off-by: Zhao Liu --- Changes Since v1: * New patch suggested by Ewan. --- target/i386/cpu.c | 5 - 1 file changed, 4 insertions(+), 1 deletion

[PATCH v2 5/9] i386/cpu: Add a "x-force-cpuid-0x1f" property

re.kernel.org/qemu-devel/ph0pr02mb738410511bf51b12db09be6cf6...@ph0pr02mb7384.namprd02.prod.outlook.com/ Signed-off-by: Manish Mishra Co-authored-by: Xiaoyao Li Signed-off-by: Xiaoyao Li [Integrated and rebased 2 previous patches (ordered by post time)] Reviewed-by: Dapeng Mi Tested-by: Yi Lai

[PATCH v2 7/9] i386/cpu: Enable 0x1f leaf for GraniteRapids by default

Host GraniteRapids CPU has 0x1f leaf by default, so that enable it for Guest CPU by default as well. Suggested-by: Igor Mammedov Reviewed-by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu --- Changes since RFC: * Rename the property to "x-force-cpuid-0x1f". (Igor) --- t

[PATCH v2 4/9] i386/cpu: Introduce cache model for YongFeng

Liu --- Changes Since v1: * Polish the note. Changes on the original codes: * Rearrange cache model fields to make them easier to check. * And add explanation of why v3 is needed. * Drop lines_per_tag field for L2 & L3. --- target/i386/cpu.c |

[PATCH v2 6/9] i386/cpu: Enable 0x1f leaf for SierraForest by default

Host SierraForest CPU has 0x1f leaf by default, so that enable it for Guest CPU by default as well. Suggested-by: Igor Mammedov Reviewed-by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu --- Changes since RFC: * Rename the property to "x-force-cpuid-0x1f". (Igor) --- target/

[PATCH v2 8/9] i386/cpu: Enable 0x1f leaf for SapphireRapids by default

Host SapphireRapids CPU has 0x1f leaf by default, so that enable it for Guest CPU by default as well. Suggested-by: Igor Mammedov Reviewed-by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu --- Changes since RFC: * Rename the property to "x-force-cpuid-0x1f". (Igor) --- t

[PATCH v2 3/9] i386/cpu: Introduce cache model for SapphireRapids

ned-off-by: Zhao Liu --- target/i386/cpu.c | 96 +++ 1 file changed, 96 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4ce063fb6492..e9f3434b096c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2881,6 +2881,97 @@ st

[PATCH v2 1/9] i386/cpu: Introduce cache model for SierraForest

Signed-off-by: Zhao Liu --- target/i386/cpu.c | 96 +++ 1 file changed, 96 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7f88fe0c8697..a97ee3c2af43 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2878,6 +2878,97 @@ st

[PATCH v2 2/9] i386/cpu: Introduce cache model for GraniteRapids

Signed-off-by: Zhao Liu --- target/i386/cpu.c | 96 +++ 1 file changed, 96 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a97ee3c2af43..4ce063fb6492 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2881,6 +2881,97 @@ st

[PATCH v2 0/9] i386/cpu: Intel cache model & topo CPUID enhencement

0401130205.2198253-34-xiaoyao...@intel.com/ Thanks and Best Regards, Zhao --- Ewan Hai (1): i386/cpu: Introduce cache model for YongFeng Manish Mishra (1): i386/cpu: Add a "x-force-cpuid-0x1f" property Zhao Liu (7): i386/cpu: Introduce cache model for SierraForest i386/cpu: Introdu

[PATCH v2 14/18] i386/cpu: Select legacy cache model based on vendor in CPUID 0x4

by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu --- target/i386/cpu.c | 43 ++- 1 file changed, 34 insertions(+), 9 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 34a82a378ccb..73872cb74b6f 100644 --- a/target/i386/cpu.c +++

[PATCH v2 15/18] i386/cpu: Select legacy cache model based on vendor in CPUID 0x80000005

PUID 0x8005 leaf, in X86CPUState, a unified cache_info is enough. It only needs to be initialized and configured with the corresponding legacy cache model based on the vendor. Cc: EwanHai Tested-by: Yi Lai Signed-off-by: Zhao Liu --- Note, side effect of this patch: fix the inconsistency cache in

[PATCH v2 05/18] i386/cpu: Consolidate CPUID 0x4 leaf

0x2 leaf. This makes sense, as in the 0x2 leaf era, all supported caches should have the corresponding descriptor. Reviewed-by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu --- Changes Since v1: * Fix the typo in comment. (Ewan) --- target/

[PATCH v2 16/18] i386/cpu: Select legacy cache model based on vendor in CPUID 0x80000006

ate, a unified cache_info is enough. It only needs to be initialized and configured with the corresponding legacy cache model based on the vendor. Tested-by: Yi Lai Signed-off-by: Zhao Liu --- target/i386/cpu.c | 36 +++- 1 file changed, 31 insertions(+), 5 deletions(-)

[PATCH v2 12/18] i386/cpu: Add legacy_amd_cache_info cache model

compatibility later. Reviewed-by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu --- target/i386/cpu.c | 112 ++ 1 file changed, 53 insertions(+), 59 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6cd942f95779..4a0505004bfb

[PATCH v2 10/18] i386/cpu: Fix CPUID[0x80000006] for Intel CPU

ME of legacy_l2_cache_amd: /*FIXME: CPUID leaf 0x8006 is inconsistent with leaves 2 & 4 */ In addition, per AMD's APM, update the comment of CPUID[0x8006]. [1]: https://lore.kernel.org/qemu-devel/c522ebb5-04d5-49c6-9ad8-d755b8998...@zhaoxin.com/ Tested-by: Yi Lai Signed-of

[PATCH v2 09/18] i386/cpu: Rename AMD_ENC_ASSOC to X86_ENC_ASSOC

CPUs.. Tested-by: Yi Lai Signed-off-by: Zhao Liu --- Changes Since v1: * Spilt this cleanup as a seperate patch. --- target/i386/cpu.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6ab199c9a112..e0d5a39e477c

[PATCH v2 02/18] i386/cpu: Add descriptor 0x49 for CPUID 0x2 encoding

e the consistent cache model, and use legacy_l2_cache as the default L2 cache. Therefore, add descriptor 0x49 to represent general L2 cache. Reviewed-by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu --- Changes Since v2: * Fix the typo in comment. (Dapeng) --- target/i386/cpu.c | 13 +++

[PATCH v2 07/18] i386/cpu: Add x-vendor-cpuid-only-v2 option for compatibility

ernal only, QEMU doesn't support "internal" property. To avoid any other unexpected issues, check the dependency. Tested-by: Yi Lai Signed-off-by: Zhao Liu --- Changes Since v1: * Split the x-vendor-cpuid-only-v2 support into a seperate pacth and make sure it depends on x-v

[PATCH v2 04/18] i386/cpu: Present same cache model in CPUID 0x2 & 0x4

", "pentium", "pentium2" and "pentium3"), because they have already had the special default cache model - legacy_intel_cpuid2_cache_info. [1]: https://lore.kernel.org/qemu-devel/5b31733c0709081227w3e5f1036odbc649edfdc8c...@mail.gmail.com/ [2]: https://lore.kernel.org/qemu-devel/478b65c8.

[PATCH v2 00/18] i386/cpu: Unify the cache model in X86CPUState

_info_amd Note: patch 11-15 they each provide more specific evidence that selecting a legacy cache model based on the Guest vendor in CPUID 0x2, 0x4, 0x8005, 0x80000006, and 0x801D leaves is both valid and safe, and doesn't break compatibility. Change Log == Changes Since v1: * Add Tested-by & Reviewed-by. * Addr

[PATCH v2 17/18] i386/cpu: Select legacy cache model based on vendor in CPUID 0x8000001D

it is acceptable to select the default legacy cache model based on the vendor. For the CPUID 0x801D leaf, in X86CPUState, a unified cache_info is enough. It only needs to be initialized and configured with the corresponding legacy cache model based on the vendor. Tested-by: Yi Lai Signed-off-

[PATCH v2 08/18] i386/cpu: Mark CPUID[0x80000005] as reserved for Intel

Tested-by: Yi Lai Signed-off-by: Zhao Liu --- Changes Since v1: * Drop lines_per_tag assertion in encode_cache_cpuid8005(). Changes Since RFC: * Only set all-0 for Intel CPU. * Add x-vendor-cpuid-only-v2. --- target/i386/cpu.c | 12 1 file changed, 8 insertions(+), 4 dele

[PATCH v2 11/18] i386/cpu: Add legacy_intel_cache_info cache model

later. Reviewed-by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu --- target/i386/cpu.c | 101 +- 1 file changed, 54 insertions(+), 47 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 609efb10ddb5..6cd942f95779 100644 --- a

[PATCH v2 18/18] i386/cpu: Use a unified cache_info in X86CPUState

in X86CPUState, and during its initialization, set different legacy cache models based on the vendor. Reviewed-by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu --- target/i386/cpu.c | 150 -- target/i386/cpu.h | 5 +- 2 files changed, 27

[PATCH v2 13/18] i386/cpu: Select legacy cache model based on vendor in CPUID 0x2

by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu --- target/i386/cpu.c | 47 +-- target/i386/cpu.h | 1 + 2 files changed, 38 insertions(+), 10 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4a0505004bfb..34a82a378ccb

[PATCH v2 01/18] i386/cpu: Refine comment of CPUID2CacheDescriptorInfo

Refer to SDM vol.3 table 1-21, add the notes about the missing descriptor, and fix the typo and comment format. Reviewed-by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu --- Changes Since v1: * Fix the typo in comment. (Dapeng) --- target/i386/cpu.c | 31

[PATCH v2 06/18] i386/cpu: Drop CPUID 0x2 specific cache info in X86CPUState

i Lai Signed-off-by: Zhao Liu --- target/i386/cpu.c | 31 +++ target/i386/cpu.h | 3 ++- 2 files changed, 13 insertions(+), 21 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 37cf591bea8d..af67f12e939d 100644 --- a/target/i386/cpu.c +++ b/target

[PATCH v2 03/18] i386/cpu: Add default cache model for Intel CPUs with level < 4

"pentium3") won't be used for migration, there's no need to add new versioned CPU models Tested-by: Yi Lai Signed-off-by: Zhao Liu --- target/i386/cpu.c | 65 +++ 1 file changed, 65 insertions(+) diff --git a/target/i386

Re: [PULL 14/19] ui/gtk: Update scales in fixed-scale mode when rendering GL area

Hi, On Fri, 2025-07-11 at 11:01 +0400, Marc-André Lureau wrote: > Hi > > On Thu, Jul 10, 2025 at 4:24 PM Peter Maydell > wrote: > > > > On Sat, 24 May 2025 at 18:37, wrote: > > > > > > From: Weifeng Liu > > > > > > When gl=on, sc

Re: [PATCH 4/4] target/i386: move accel_cpu_instance_init to .instance_init

ore.kernel.org/qemu-devel/afpocftpblb34...@intel.com/ > Signed-off-by: Paolo Bonzini > --- > target/i386/cpu.c | 8 ++++ > 1 file changed, 4 insertions(+), 4 deletions(-) LGTM, Reviewed-by: Zhao Liu

Re: [PATCH 3/4] target/i386: allow reordering max_x86_cpu_initfn vs accel CPU init

> > Signed-off-by: Paolo Bonzini > --- > target/i386/cpu.c | 24 > target/i386/kvm/kvm-cpu.c | 2 ++ > 2 files changed, 14 insertions(+), 12 deletions(-) Reviewed-by: Zhao Liu

Re: [PATCH 2/4] target/i386: nvmm, whpx: add accel/CPU class that sets host vendor

On Fri, Jul 11, 2025 at 02:06:01AM +0200, Paolo Bonzini wrote: > Date: Fri, 11 Jul 2025 02:06:01 +0200 > From: Paolo Bonzini > Subject: [PATCH 2/4] target/i386: nvmm, whpx: add accel/CPU class that sets > host vendor > X-Mailer: git-send-email 2.50.0 > > NVMM and WHPX are virtualizers, and there

Re: [PATCH 1/4] target/i386: move max_features to class

-cpu.c | 3 ++- > target/i386/kvm/kvm-cpu.c | 5 +++-- > 4 files changed, 9 insertions(+), 6 deletions(-) Reviewed-by: Zhao Liu

[PATCH] qga: Fix truncated output handling in guest-exec status reporting

From: "minglei.liu" Signed-off-by: minglei.liu --- qga/commands.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qga/commands.c b/qga/commands.c index 5a5fad31f8..5f20af25d3 100644 --- a/qga/commands.c +++ b/qga/commands.c @@ -205,13 +205,15 @@ GuestExecStatus *qmp_gu

Re: [PATCH v9 2/2] hw/i386: Add the ramfb romfile compatibility

gt; Reviewed-by: Eric Auger > Signed-off-by: Shaoqin Huang > --- > hw/core/machine.c | 2 ++ > hw/display/ramfb-standalone.c | 2 +- > hw/i386/microvm.c | 3 +++ > hw/i386/pc_piix.c | 10 ++ > hw/i386/pc_q35.c | 3 +++ > hw/vfio/pci.c | 2 +- > 6 files changed, 20 insertions(+), 2 deletions(-) Reviewed-by: Zhao Liu

Re: [PATCH v9 1/2] ramfb: Add property to control if load the romfile

gt; include/hw/display/ramfb.h| 2 +- > 7 files changed, 13 insertions(+), 7 deletions(-) LGTM, Reviewed-by: Zhao Liu

Re: [PATCH] target/i386: Add TSA feature flags

On Thu, Jul 10, 2025 at 10:57:49AM +0800, Xiaoyao Li wrote: > Date: Thu, 10 Jul 2025 10:57:49 +0800 > From: Xiaoyao Li > Subject: Re: [PATCH] target/i386: Add TSA feature flags [snip] > > I recommend splitting this into two separate patches: > > a. One patch to introduce the new bit 0021_EAX_VE

Re: [PATCH-for-10.1 v6 10/14] hw/core/null-machine: Define machine as generic QOM type

ouvier > --- > hw/core/null-machine.c | 14 -- > 1 file changed, 12 insertions(+), 2 deletions(-) Reviewed-by: Zhao Liu

Re: [PATCH-for-10.1 v6 02/14] qemu/target-info: Factor target_arch() out

et-info-qapi.h | 21 + > include/qemu/target-info.h | 2 +- > hw/core/machine-qmp-cmds.c | 8 +++- > target-info.c | 8 ++++++++ > 4 files changed, 33 insertions(+), 6 deletions(-) > create mode 100644 include/qemu/target-info-qapi.h Reviewed-by: Zhao Liu

Re: [PATCH v14 2/7] hw/core/machine: topology functions capabilities added

e cache level... > +return true; > + } > + ...at least for now, this is fine for me. We can think of how to organize everything better afterwards. So, Reviewed-by: Zhao Liu

Re: [PATCH 2/3] memattrs.h: make MemTxAttrs into enum

l allow bindgen to > generate a bitflag using the enum variants as its domain of values. > > Signed-off-by: Manos Pitsidianakis > --- > include/exec/memattrs.h | 11 ++- > 1 file changed, 6 insertions(+), 5 deletions(-) Reviewed-by: Zhao Liu

Re: [PATCH 3/3] rust: add *_with_attrs methods to MemoryRegionOps

- > 2 files changed, 52 insertions(+), 1 deletion(-) Fine for me, Reviewed-by: Zhao Liu

Re: [PATCH 1/3] rust/memory: replace size arg with Bits enum

++--- > rust/qemu-api/src/memory.rs | 34 -- > 3 files changed, 35 insertions(+), 21 deletions(-) LGTM, Reviewed-by: Zhao Liu

Re: [PATCH v2] i386/cpu: Remove FEAT_24_0_EBX for AVX10

86/cpu.c | 37 ++------- > target/i386/cpu.h | 12 > 2 files changed, 2 insertions(+), 47 deletions(-) LGTM, Reviewed-by: Zhao Liu

Re: [PATCH 2/3] memattrs.h: make MemTxAttrs into enum

l allow bindgen to > generate a bitflag using the enum variants as its domain of values. > > Signed-off-by: Manos Pitsidianakis > --- > include/exec/memattrs.h | 11 ++- > 1 file changed, 6 insertions(+), 5 deletions(-)> Reviewed-by: Zhao Liu

Re: [PATCH 1/3] rust/memory: replace size arg with Bits enum

++--- > rust/qemu-api/src/memory.rs | 34 -- > 3 files changed, 35 insertions(+), 21 deletions(-) LGTM, Reviewed-by: Zhao Liu

Re: [PATCH] i386/cpu: Remove FEAT_24_0_EBX for AVX10

On Fri, Jul 04, 2025 at 10:45:04PM +0800, Xiaoyao Li wrote: > Date: Fri, 4 Jul 2025 22:45:04 +0800 > From: Xiaoyao Li > Subject: [PATCH] i386/cpu: Remove FEAT_24_0_EBX for AVX10 > X-Mailer: git-send-email 2.43.0 > > Intel AVX10 spec has been updated to make the bit 16-18 of Th

Re: [PATCH 2/2] rust/qemu-api-macros: add unit tests

($derive_fn:ident, $input:expr, $($expected:tt)*) => {{ > +let input: proc_macro2::TokenStream = $input; > +let expected: proc_macro2::TokenStream = $($expected)*; > +let derive_fn: fn(input: syn::DeriveInput) -> > Result = > +$derive_fn; > + > +let input: syn::DeriveInput = syn::parse2(input).unwrap(); > +let result = derive_fn(input).unwrap(); > +assert_eq!(result.to_string(), expected.to_string()); > +}}; > +} Good examples to test macros. LGTM, Reviewed-by: Zhao Liu

Re: [PATCH 0/2] rust: add Derive macro unit tests

> You can run the added tests directly with this meson command: > > meson test rust-qemu-api-macros-tests Hi Manos, do you meet this error: Traceback (most recent call last): File "/usr/lib/python3/dist-packages/mesonbuild/mesonmain.py", line 146, in run return options.run_func(options)

Re: [PATCH 1/2] rust/qemu-api-macros: normalize TryInto output

--- > rust/qemu-api-macros/src/lib.rs | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Zhao Liu

Re: [PATCH v6 05/39] accel/kvm: Remove kvm_init_cpu_signals() stub

b0 ("cpus: extract out kvm-specific code > to accel/kvm") the kvm_init_cpu_signals() stub is not necessary. > > Signed-off-by: Philippe Mathieu-Daudé > Reviewed-by: Richard Henderson > --- > accel/stubs/kvm-stub.c | 5 - > 1 file changed, 5 deletions(-) Reviewed-by: Zhao Liu

Re: [PATCH v6 34/39] accel/kvm: Directly pass KVMState argument to do_kvm_create_vm()

; > Signed-off-by: Philippe Mathieu-Daudé > Reviewed-by: Richard Henderson > --- > accel/kvm/kvm-all.c | 7 ++- > 1 file changed, 2 insertions(+), 5 deletions(-) Reviewed-by: Zhao Liu

Re: [PATCH v6 33/39] accel: Directly pass AccelState argument to AccelClass::has_memory()

gt; > Reviewed-by: Richard Henderson > Signed-off-by: Philippe Mathieu-Daudé > --- > include/qemu/accel.h | 2 +- > accel/kvm/kvm-all.c | 4 ++-- > system/memory.c | 2 +- > 3 files changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Zhao Liu

Re: [PATCH v6 36/39] accel: Pass AccelState argument to gdbstub_supported_sstep_flags()

hvf-all.c | 2 +- > accel/kvm/kvm-all.c | 2 +- > accel/tcg/tcg-all.c | 2 +- > 5 files changed, 5 insertions(+), 5 deletions(-) Make sense. I think then MachineClass can also be similarly cleaned up. Reviewed-by: Zhao Liu

Re: [PATCH v6 33/39] accel: Directly pass AccelState argument to AccelClass::has_memory()

gt; > Reviewed-by: Richard Henderson > Signed-off-by: Philippe Mathieu-Daudé > --- > include/qemu/accel.h | 2 +- > accel/kvm/kvm-all.c | 4 ++-- > system/memory.c | 2 +- > 3 files changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Zhao Liu

Re: [PATCH v6 34/39] accel/kvm: Directly pass KVMState argument to do_kvm_create_vm()

; > Signed-off-by: Philippe Mathieu-Daudé > Reviewed-by: Richard Henderson > --- > accel/kvm/kvm-all.c | 7 ++- > 1 file changed, 2 insertions(+), 5 deletions(-) Reviewed-by: Zhao Liu

Re: [PATCH v6 35/39] accel: Remove unused MachineState argument of AccelClass::setup_post()

athieu-Daudé > Reviewed-by: Richard Henderson > --- > include/qemu/accel.h | 2 +- > accel/accel-system.c | 2 +- > accel/xen/xen-all.c | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Zhao Liu

Re: [PATCH v6 32/39] accel/tcg: Prefer local AccelState over global current_accel()

; > Signed-off-by: Philippe Mathieu-Daudé > Reviewed-by: Richard Henderson > --- > accel/tcg/tcg-all.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Zhao Liu

Re: [PATCH v6 31/39] accel/kvm: Prefer local AccelState over global MachineState::accel

; > Signed-off-by: Philippe Mathieu-Daudé > Reviewed-by: Richard Henderson > --- > accel/kvm/kvm-all.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) Reviewed-by: Zhao Liu

Re: [PATCH v6 30/39] accel: Propagate AccelState to AccelClass::init_machine()

>accelerator", so that we could get @accel by ms->accelerator. But considerring the user emulation, where the @ms is NULL, and for these cases, it needs to bring current_accel() back in patch 32. Anyway, this solution is also fine for me, so, Reviewed-by: Zhao Liu ...But there'

Re: [PATCH v6 29/39] accel: Keep reference to AccelOpsClass in AccelClass

| 1 + > accel/accel-system.c | 3 ++- > accel/tcg/tcg-accel-ops.c | 4 +++- > 5 files changed, 11 insertions(+), 3 deletions(-)> Reviewed-by: Zhao Liu

Re: [PATCH v6 27/39] accel: Pass old/new interrupt mask to handle_interrupt() handler

- > include/system/accel-ops.h | 2 +- > accel/tcg/tcg-accel-ops-icount.c | 8 +++- > accel/tcg/tcg-accel-ops.c| 4 +--- > system/cpus.c| 12 +++- > 6 files changed, 14 insertions(+), 16 deletions(-) Reviewed-by: Zhao Liu

Re: [PATCH v6 26/39] accel/dummy: Extract 'dummy-cpus.h' header from 'system/cpus.h'

y-cpus.h| 14 ++ > include/system/cpus.h | 5 - > accel/dummy-cpus.c| 1 + > accel/qtest/qtest.c | 1 + > accel/xen/xen-all.c | 1 + > 6 files changed, 18 insertions(+), 5 deletions(-) > create mode 100644 accel/dummy-cpus.h Reviewed-by: Zhao Liu

Re: [PATCH v6 25/39] accel/whpx: Expose whpx_enabled() to common code

-stub.c | 12 > target/i386/whpx/whpx-all.c | 7 +-- > accel/stubs/meson.build | 1 + > 4 files changed, 28 insertions(+), 19 deletions(-) > create mode 100644 accel/stubs/whpx-stub.c Reviewed-by: Zhao Liu

Re: [PATCH v6 24/39] accel/nvmm: Expose nvmm_enabled() to common code

.c | 12 > target/i386/nvmm/nvmm-all.c | 8 +--- > accel/stubs/meson.build | 1 + > 4 files changed, 26 insertions(+), 18 deletions(-) > create mode 100644 accel/stubs/nvmm-stub.c With header file fixed, Reviewed-by: Zhao Liu

Re: [PATCH v6 23/39] accel/system: Document cpu_synchronize_state_post_init/reset()

; > Signed-off-by: Philippe Mathieu-Daudé > Reviewed-by: Richard Henderson > --- > include/system/accel-ops.h | 8 > include/system/hw_accel.h | 8 > 2 files changed, 16 insertions(+) Reviewed-by: Zhao Liu

Re: [PATCH v6 22/39] accel/system: Document cpu_synchronize_state()

ippe Mathieu-Daudé > Reviewed-by: Richard Henderson > --- > include/system/accel-ops.h | 8 > include/system/hw_accel.h | 13 +++-- > 2 files changed, 19 insertions(+), 2 deletions(-)> Reviewed-by: Zhao Liu

Re: [PATCH v6 21/39] accel/kvm: Remove kvm_cpu_synchronize_state() stub

: Richard Henderson > --- > accel/stubs/kvm-stub.c | 4 > 1 file changed, 4 deletions(-) Reviewed-by: Zhao Liu

Re: [PATCH v6 20/39] accel/whpx: Replace @dirty field by generic CPUState::vcpu_dirty field

gt; > No need for accel-specific @dirty field when we have > a generic one in CPUState. > > Signed-off-by: Philippe Mathieu-Daudé > Reviewed-by: Richard Henderson > --- > target/i386/whpx/whpx-all.c | 23 +++ > 1 file changed, 11 insertions(+), 12 deletions(-) Reviewed-by: Zhao Liu

Re: [PATCH v6 19/39] accel/nvmm: Replace @dirty field by generic CPUState::vcpu_dirty field

gt; > No need for accel-specific @dirty field when we have > a generic one in CPUState. > > Signed-off-by: Philippe Mathieu-Daudé > Reviewed-by: Richard Henderson > --- > target/i386/nvmm/nvmm-all.c | 21 ++--- > 1 file changed, 10 insertions(+), 11 deletions(-) Reviewed-by: Zhao Liu

Re: [PATCH v6 18/39] accel/hvf: Replace @dirty field by generic CPUState::vcpu_dirty field

hvf.c | 4 ++-- > target/i386/hvf/hvf.c | 4 ++-- > target/i386/hvf/x86hvf.c | 2 +- > 5 files changed, 10 insertions(+), 11 deletions(-) Reviewed-by: Zhao Liu

Re: [PATCH v6 16/39] accel/hvf: Move generic method declarations to hvf-all.c

> accel/hvf/hvf-all.c | 268 + > 2 files changed, 272 insertions(+), 270 deletions(-) Reviewed-by: Zhao Liu

Re: [PATCH v6 15/39] accel/hvf: Move per-cpu method declarations to hvf-accel-ops.c

+ > accel/hvf/hvf-all.c | 28 > 2 files changed, 30 insertions(+), 28 deletions(-) Reviewed-by: Zhao Liu

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