backend->guest_memfd is true, to
allow shm memory backend serve as shared memory for coco-VMs.
cc: Stefano Garzarella
Signed-off-by: Xiaoyao Li
---
backends/hostmem-shm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/backends/hostmem-shm.c b/backends/hostmem-shm.c
index f66211a2ec92..806e2670
On 7/17/2025 1:28 AM, Philippe Mathieu-Daudé wrote:
Developers are custom to read RWX, not RWE.
Replace E -> X.
Reported-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Xiaoyao Li
---
accel/hvf/hvf-all.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
d
dre Chartre
Suggested-by: Daniel P. Berrangé
Signed-off-by: Paolo Bonzini
Reviewed-by: Xiaoyao Li
This looks reasonable to me.
Though it will break the usecase of people boot VM with "-cpu
AMD-model,+arch_capabilities", like in [1], I think it's OK break it and
force people to
On 7/17/2025 6:39 PM, Paolo Bonzini wrote:
Take tdx_guest->lock when injecting the event notification interrupt into
the guest.
Fixes CID 1612364.
Reported-by: Peter Maydell
Cc: Xiaoyao Li
Signed-off-by: Paolo Bonzini
Reviewed-by: Xiaoyao Li
---
target/i386/kvm/tdx.c |
Commit 40da501d8989 ("i386/tdx: handle TDG.VP.VMCALL") added
redundant qemu_mutex_init(&tdx->lock) in tdx_guest_init by mistake.
Fix it by removing the redundant one.
Fixes: 40da501d8989 ("i386/tdx: handle TDG.VP.VMCALL")
Reported-by: Peter Maydell
Signed-off-by: X
On 7/17/2025 5:46 PM, Peter Maydell wrote:
On Mon, 14 Jul 2025 at 12:13, Paolo Bonzini wrote:
From: Xiaoyao Li
Record the interrupt vector and the apic id of the vcpu that calls
TDVMCALL_SETUP_EVENT_NOTIFY_INTERRUPT.
Inject the interrupt to TD guest to notify the completion of
when notify
On 7/17/2025 5:40 PM, Peter Maydell wrote:
On Fri, 30 May 2025 at 08:23, Paolo Bonzini wrote:
From: Xiaoyao Li
Invoke KVM_TDX_INIT_VM in kvm_arch_pre_create_vcpu() that
KVM_TDX_INIT_VM configures global TD configurations, e.g. the canonical
CPUID config, and must be executed prior to
On 7/16/2025 3:15 PM, Cédric Le Goater wrote:
Recent changes broke build on 32-bit host. Since there is no 32-bit
support, restrict SEV to 64-bit.
Signed-off-by: Cédric Le Goater
Reviewed-by: Xiaoyao Li
---
hw/i386/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
;target/i386: move accel_cpu_instance_init to
.instance_init")
Reported-by: Paolo Abeni
Tested-by: Paolo Abeni
Signed-off-by: Zhao Liu
Reviewed-by: Xiaoyao Li
Hi Michael,
On Wed, 16 Jul 2025 19:42:42 +0800 Michael S. Tsirkin
wrote ---
> On Wed, Jul 16, 2025 at 07:41:11PM +0800, Li Chen wrote:
> > Hi Michael,
> >
> > Thanks for your kind review! All issues below have been fixed in v5:
> > https:/
28, 2025 at 06:53:38PM +0800, Li Chen wrote:
> > From: Li Chen
> >
> > The virt machines always instantiate a PL011/16550 at UART0 and
> > describe it in ACPI (DSDT device node plus optional SPCR table). When
> > the command line contains “-serial none” there is
From: Li Chen
The virt machines always instantiate a PL011/16550 at UART0 and
describe it in ACPI (DSDT device node plus optional SPCR table). When
the command line contains “-serial none” there is no backend attached to
that UART, yet the guest still discovers it via ACPI and may try to use
it
From: Li Chen
Add ACPI SPCR table test case for RISC-V when SPCR was off.
Signed-off-by: Li Chen
Reviewed-by: Sunil V L
---
Notes:
Changes since v3: Add Reviewed-by from Sunil V L
tests/qtest/bios-tables-test.c | 22 ++
1 file changed, 22 insertions(+)
diff --git
From: Li Chen
Add ACPI SPCR table test case for ARM when SPCR was off.
Signed-off-by: Li Chen
---
tests/qtest/bios-tables-test.c | 20
1 file changed, 20 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 4dbc07ec5e
From: Li Chen
The ACPI SPCR (Serial Port Console Redirection) table allows firmware
to specify a preferred serial console device to the operating system.
On ARM64 systems, Linux by default respects this table: even if the
kernel command line does not include a hardware serial console (e.g
From: Li Chen
This series introduces a new machine option, spcr=on|off, allowing users
to disable the ACPI SPCR (Serial Port Console Redirection) table.
By default, SPCR is enabled. Disabling it can help ensure that the guest's
console behavior is determined solely by kernel command
The implementation of host_cpu_max_instance_init() was merged into
host_cpu_instance_init() by commit 29f1ba338baf ("target/i386: merge
host_cpu_instance_init() and host_cpu_max_instance_init()"), while the
declaration of it remains in host-cpu.h.
Clean it up.
Signed-off-by:
them from source to header.
Suggested-by: Xiaoyao Li
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Xiaoyao Li
---
Based-on: <20250703173248.44995-4-phi...@linaro.org>
---
include/system/runstate.h | 30 ++
system/runstate.c
-transient-scheduler-attacks.pdf
Co-developed-by: Borislav Petkov (AMD)
Signed-off-by: Borislav Petkov (AMD)
Signed-off-by: Babu Moger
Reviewed-by: Xiaoyao Li
: Borislav Petkov (AMD)
Signed-off-by: Babu Moger
Reviewed-by: Xiaoyao Li
72
CPU #1: thread_id=42916 model=cortex-a72
CPU #2: thread_id=42916 model=cortex-r5f
CPU #3: thread_id=42916 model=cortex-r5f
(qemu)
Reviewed-by: Richard Henderson
Reviewed-by: Zhao Liu
Tested-by: Zhao Liu
Signed-off-by: Philippe Mathieu-Daudé
IIRC, I gave r-b tag before. An
On 7/15/2025 5:02 PM, Alex Bennée wrote:
Xiaoyao Li writes:
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
---
include/system/runstate.h | 10 ++
1 file changed, 10 insertions
On 7/15/2025 5:06 PM, Philippe Mathieu-Daudé wrote:
Knowing the QOM type name of a CPU can be useful,
in particular to infer its model name.
Reviewed-by: Richard Henderson
Reviewed-by: Zhao Liu
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Xiaoyao Li
---
qapi/machine.json
On 7/15/2025 3:15 PM, Philippe Mathieu-Daudé wrote:
"hw/xen/arch_hvm.h" only declares the arch_handle_ioreq() and
arch_xen_set_memory() prototypes, which are not used by xen-pvh.c.
Remove the unnecessary header inclusion.
Cc: Xiaoyao Li
Signed-off-by: Philippe Mathieu-Daudé
R
need for seperate non-gmem memory because gmem
itself can be served as shared memory. So that we can introduce
memory-backend-guestmemfd as the specific backend for in-place
conversion gmem.
Signed-off-by: Yan Zhao
Co-developed-by Xiaoyao Li
Signed-off-by: Xiaoyao Li
---
accel/kvm/kvm-all.c
kernel.org/all/ag0pnijvpl0cz...@google.com/
Signed-off-by: Xiaoyao Li
---
include/system/memory.h | 3 +++
system/memory.c | 2 +-
system/physmem.c| 8 +---
3 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/include/system/memory.h b/include/system/memo
nge.
Please go to each patch (specifically patch 3/4/5) to discuss the ABI
usage, potential issue, and maybe the upstreamable design.
[1] https://lore.kernel.org/all/cover.1747264138.git.ackerley...@google.com/
[2] https://lore.kernel.org/all/20250424030033.32635-1-yan.y.z...@intel.com/
Xiaoyao L
Signed-off-by: Xiaoyao Li
---
linux-headers/linux/guestmem.h | 29 +
linux-headers/linux/kvm.h | 18 ++
2 files changed, 47 insertions(+)
create mode 100644 linux-headers/linux/guestmem.h
diff --git a/linux-headers/linux/guestmem.h b/linux
mable solution, the hugetlb support of gmem can be
implemented as "hugetlb" and "hugetlbsize" properties of
memory-backend-guestmemfd as similar of memory-backend-memfd. (It
requires memory-backed-guestmemfd introduced for in-place conversion
gmem at first)
Signed-off-by: Xiaoy
Signed-off-by: Xiaoyao Li
---
scripts/update-linux-headers.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
index b43b8ef75a63..3f6169a121a8 100755
--- a/scripts/update-linux-headers.sh
+++ b/scripts/update
"confidential-guest-support" is the recommended property instead of
"memory-encryption". Switch to "confidential-guest-support" in the
example of sev-guest.
Signed-off-by: Xiaoyao Li
---
qemu-options.hx | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
s of it and not recommended.
Signed-off-by: Xiaoyao Li
---
qemu-options.hx | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/qemu-options.hx b/qemu-options.hx
index 27b7b79c6cad..5c400114c2e5 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -36,7 +36,8 @@ DEF
It's weird to only put sgx-epc option in "M" while leaving others to
"machine". Besides currently in qemu-manpage.html, the "sgx-epc" option
is listed at the same level of "-machine", which looks incorrect.
Move "sgx-epc" ontion to &quo
t-support"
in the comment of struct SevGuestState, just drop the example for
simplicity.
Signed-off-by: Xiaoyao Li
---
target/i386/sev.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/i386/sev.c b/target/i386/sev.c
index 1a12f0671cc6..b1831e9ab14e 100644
--- a/target/i386/sev.c
+
On 7/14/2025 5:19 PM, Xiaoyao Li wrote:
Patch 1 is the fix to generated doc html.
Patch 2-4 are the cleanup of memory-encryption
Patch 5 add description of tdx-guest.
get_maintainer.pl doesn't provide me the maintainer of qemu-options.hx.
I have to send the series to the folks I'
Patch 1 is the fix to generated doc html.
Patch 2-4 are the cleanup of memory-encryption
Patch 5 add description of tdx-guest.
Xiaoyao Li (5):
qemu-options: Move sgx-epc options from "M" to "machine"
i386/sev: Remove the example that references memory-encryption
Add description of tdx-guest object so that QEMU doc page can have the
description.
Signed-off-by: Xiaoyao Li
---
qemu-options.hx | 40
1 file changed, 40 insertions(+)
diff --git a/qemu-options.hx b/qemu-options.hx
index 5c400114c2e5..50c7874bbce9
.
Reviewed-by: Zhao Liu
Signed-off-by: Guixiong Wei
Signed-off-by: Yipeng Yin
Signed-off-by: Chuang Xu
Signed-off-by: Zhao Liu
Reviewed-by: Xiaoyao Li
On 7/14/2025 4:08 PM, Zhao Liu wrote:
Per SDM,
8008H EAX Linear/Physical Address size.
Bits 07-00: #Physical Address Bits*.
Bits 15-08: #Linear Address Bits.
Bits 31-16: Reserved = 0.
EBX Bits 08-00: Reserved = 0.
Bit 09:
to encode vendor.
Reviewed-by: Tao Su
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
Reviewed-by: Xiaoyao Li
On 7/11/2025 3:55 PM, Paolo Bonzini wrote:
Simplify the accelerators' cpu_instance_init callbacks by doing all
host-cpu setup in a single function.
btw, it changes the behavior for "-cpu base" with accelerator.
I think it should be OK considering "-cpu base" seems only for
experiment case.
On 7/11/2025 3:55 PM, Paolo Bonzini wrote:
Simplify the accelerators' cpu_instance_init callbacks by doing all
host-cpu setup in a single function.
Based-on: <20250711000603.438312-1-pbonz...@redhat.com>
Cc: Xiaoyao Li
Signed-off-by: Paolo Bonzini
Miss to remove the declaration.
On 7/11/2025 2:35 PM, Paolo Bonzini wrote:
Il ven 11 lug 2025, 04:18 Xiaoyao Li ha scritto:
Besides, do we need to call host_cpu_max_instance_init() for the case of
xcc->max_features, like what has been done for kvm and hvf?
I am intentionally skipping that because it would not have
Hypervisor.framework, because
KVM sets it *after* the user's value is set by DeviceState's
intance_post_init callback.
Reported-by: Xiaoyao Li
Signed-off-by: Paolo Bonzini
Reviewed-by: Xiaoyao Li
BTW, the user's value of "pmu" and "invtsc" are still broken for TDX
max_x86_cpu_initfn
after accelerator init.
Signed-off-by: Paolo Bonzini
Reviewed-by: Xiaoyao Li
---
target/i386/cpu.c | 24
target/i386/kvm/kvm-cpu.c | 2 ++
2 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
On 7/11/2025 8:06 AM, Paolo Bonzini wrote:
NVMM and WHPX are virtualizers, and therefore they need to use
(at least by default) the host vendor for the guest CPUID.
Add a cpu_instance_init implementation to these accelerators.
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 8
On 7/11/2025 8:06 AM, Paolo Bonzini wrote:
NVMM and WHPX are virtualizers, and therefore they need to use
(at least by default) the host vendor for the guest CPUID.
Add a cpu_instance_init implementation to these accelerators.
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 8
ite features
* set using QOM properties, and we can convert
* plus_features & minus_features to global properties
* inside x86_cpu_parse_featurestr() too.
with above added,
Reviewed-by: Xiaoyao Li
There is actually the .has_gpa field when translating the QAPI data
type GuestPanicInformationTdx to C structure.
Stop using the magic number -1 as the indicator for no valid gpa.
Instead just use .has_gpa field.
Signed-off-by: Xiaoyao Li
---
system/runstate.c | 2 +-
target/i386/kvm/tdx.c
On 7/10/2025 10:11 PM, Daniel P. Berrangé wrote:
On Thu, Jul 10, 2025 at 10:06:10PM +0800, Xiaoyao Li wrote:
On 7/10/2025 7:40 PM, Xiaoyao Li wrote:
On 7/10/2025 11:55 AM, Zhenzhong Duan wrote:
Gpa is defined in QAPI but never reported to monitor because has_gpa is
never set to ture.
Fix it
On 7/10/2025 7:40 PM, Xiaoyao Li wrote:
On 7/10/2025 11:55 AM, Zhenzhong Duan wrote:
Gpa is defined in QAPI but never reported to monitor because has_gpa is
never set to ture.
Fix it by setting has_gpa to ture when TDX_REPORT_FATAL_ERROR_GPA_VALID
is set in error_code.
Hi Zhenzhong,
I would
On 7/10/2025 8:27 PM, Peter Maydell wrote:
On Fri, 30 May 2025 at 08:23, Paolo Bonzini wrote:
From: Xiaoyao Li
Some CPUID bits are controlled by XFAM. They are not covered by
tdx_caps.cpuid (which only contians the directly configurable bits), but
they are actually supported when the
On 7/10/2025 11:55 AM, Zhenzhong Duan wrote:
Gpa is defined in QAPI but never reported to monitor because has_gpa is
never set to ture.
Fix it by setting has_gpa to ture when TDX_REPORT_FATAL_ERROR_GPA_VALID
is set in error_code.
Hi Zhenzhong,
I would like to understand what the problem is wi
On 7/9/2025 11:02 PM, Moger, Babu wrote:
Hi Boris,
On 7/9/25 05:49, Borislav Petkov (AMD) wrote:
Hi,
I *think* this is how it should be done but I might be forgetting something.
It seems to work in my testing here.
Babu, double-check me pls.
Thx.
Patch looks good. Few comments.
Is KVM aw
I will continue looking after the TDX code in QMEU.
Add a specific entry for TDX and add myself as the reviewer.
Signed-off-by: Xiaoyao Li
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1842c3dd83fb..3937faf700f7 100644
--- a
AT_24_0_EBX and related stuff. Just hardcore
the bits to all 1 when AVX10 is exposed to guest, to comply with the SDM
and stop trying to associate them with the enumeration of vector length.
[1] https://cdrdv2.intel.com/v1/dl/getContent/671200 (rev 088)
Signed-off-by: Xiaoyao Li
---
changes in v2
On 7/6/2025 6:06 PM, Zhao Liu wrote:
On Fri, Jul 04, 2025 at 10:45:04PM +0800, Xiaoyao Li wrote:
Date: Fri, 4 Jul 2025 22:45:04 +0800
From: Xiaoyao Li
Subject: [PATCH] i386/cpu: Remove FEAT_24_0_EBX for AVX10
X-Mailer: git-send-email 2.43.0
Intel AVX10 spec has been updated to make the bit 16
allow the
configurability of the bits anymore. So just remove the leaf
FEAT_24_0_EBX and related stuff and hardcore the bits to all 1 when
AVX10 is exposed to guest.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 36 +---
target/i386/cpu.h | 12
2
On 7/4/2025 10:45 PM, Xiaoyao Li wrote:
Intel AVX10 spec has been updated to make the bit 16-18 of
CPUID.24_0.EBX as reserved at 1 because all the Intel processors with
AVX10 support will support all the vector lengths.
FYI. The latest AVX10 spec:
https://cdrdv2.intel.com/v1/dl/getContent
On 7/4/2025 4:20 PM, Zhao Liu wrote:
yes, QEMU supports separate address space for SMM mode with KVM. It's just
that QEMU doesn't connect it with the CPU address space.
Yes, you're right.
(But initially, it might have been intentional, as KVM's SMM address
space is global. It is consistent wit
: Xiaoyao Li
not calling a hidden handler under
the hood. Make AccelOpsClass::handle_interrupt() mandatory.
Expose generic_handle_interrupt() prototype and register it
for each accelerator.
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Update CPUState::interrupt_request once in cpu_interrupt().
Pass the old and new masks along.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/tcg/tcg-accel-ops-icount.h | 2 +-
accel/tcg/tcg-accel-ops.h
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
'dummy' helpers are specific to accelerator implementations,
no need to expose them via "system/cpus.h".
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
BTW, as what you do for HVF in this series that moving vcpu methods from
hvf-all.c to hvf-accel-ops.c, do you plan to move
kvm_cpu_synchronize_state() from kvm-all.c to kvm-accel-ops.c ?
---
accel/stubs/kvm
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
No need for accel-specific @dirty field when we have
a generic one in CPUState.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
No need for accel-specific @dirty field when we have
a generic one in CPUState.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
No need for accel-specific @dirty field when we have
a generic one in CPUState.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
---
include/hw/core/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/hw/core/cpu.h b
Reviewed-by: Xiaoyao Li
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
AccelOpsClass is for methods dealing with vCPUs.
When only dealing with AccelState, AccelClass is sufficient.
Move cpus_are_resettable() declaration to accel/accel-system.c.
I don't think this is necessary unless a solid justfication provided.
kvm_supports_guest_debug() scope.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
On 7/4/2025 12:27 PM, Xiaoyao Li wrote:
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
---
accel/tcg/monitor.c | 27 +--
1 file changed, 17 insertions(+), 10
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
---
accel/tcg/monitor.c | 27 +--
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/accel/tcg/monitor.c
: Philippe Mathieu-Daudé
Acked-by: Dr. David Alan Gilbert
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
TCG profiler was removed in commit 1b65b4f54c7.
Fixes: 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER")
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
kvm_create_vcpu() is only used within the same file unit.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
---
include/system/kvm.h | 8
accel/kvm/kvm-all.c | 8 +++-
2 files
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Since commit 57038a92bb0 ("cpus: extract out kvm-specific code
to accel/kvm") the kvm_init_cpu_signals() stub is not necessary.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
BTW, i
oid cpu_interrupt(CPUState *cpu, int mask)
{
+g_assert(bql_locked());
The best result is it doesn't break any thing. But it can surely help
catch the case without bql locked and get the case fixed them.
So
Reviewed-by: Xiaoyao Li
if (cpus_accel->handl
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
---
include/system/runstate.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/system/runstate.h b/include/system/runstate.
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Commit 8c56c1a592b ("memory: emulate ioeventfd") added a !KVM
check because the only accelerator available back then were TCG,
QTest and KVM. Then commit 126e7f78036 ("kvm: require
KVM_CAP_IOEVENTFD and KVM_CAP_IOEVENTFD_ANY_LENGTH") suggested
'!
PU #1: thread_id=42916 (cortex-a72)
CPU #2: thread_id=42916 (cortex-r5f)
CPU #3: thread_id=42916 (cortex-r5f)
(qemu)
wow, it's really useful to the architectures can run with multiple CPU
cores.
Reviewed-by: Xiaoyao Li
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richa
On 7/3/2025 5:25 PM, Kirill Martynov wrote:
Hi, Xiaoyao!
Hi, Zhao!
Thank you for your feedback.
You wrote:
QEMU allocates separate KVM address space for SMM in register_smram_listener().
But the address space doesn't associated with cpu's address space.
The address space allocated in register
On 7/3/2025 11:08 AM, Zhao Liu wrote:
On Thu, Jul 03, 2025 at 09:03:10AM +0800, Xiaoyao Li wrote:
Date: Thu, 3 Jul 2025 09:03:10 +0800
From: Xiaoyao Li
Subject: Re: [Regression] Re: [PULL 35/35] qom: reverse order of
instance_post_init calls
On 7/3/2025 2:54 AM, Paolo Bonzini wrote:
Il mer
Record the interrupt vector and the apic id of the vcpu that calls
TDVMCALL_SETUP_EVENT_NOTIFY_INTERRUPT.
Inject the interrupt to TD guest to notify the completion of
when notify interrupt vector is valid.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/kvm.c | 3 +++
target/i386/kvm/tdx
KVM reports the supported TDVMCALL sub leafs in TDX capabilities.
one for kernel-supported
TDVMCALLs (userspace can set those blindly) and one for user-supported
TDVMCALLs (userspace can set those if it knows how to handle them)
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.c | 11
To fetch the update of TDX
Signed-off-by: Xiaoyao Li
---
linux-headers/asm-x86/kvm.h | 8 +++-
linux-headers/linux/kvm.h | 4
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h
index cd275ae76d25..f0c1a730d9c3
: Xiaoyao Li
---
target/i386/kvm/tdx.c | 6 --
target/i386/kvm/tdx.h | 2 --
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c
index e809e4b2dfa2..8c661c3ecfdb 100644
--- a/target/i386/kvm/tdx.c
+++ b/target/i386/kvm/tdx.c
@@ -1259,13
They based on
the KVM patches you put in KVM tree master.
Xiaoyao Li (4):
i386/tdx: Remove enumeration of GetQuote in
tdx_handle_get_tdvmcall_info()
update Linux headers to KVM tree master
i386/tdx: Set value of based on capabilities of both
KVM and QEMU
i386/tdx: h
On 7/3/2025 2:54 AM, Paolo Bonzini wrote:
Il mer 2 lug 2025, 09:25 Xiaoyao Li ha scritto:
IIRC that's on rhel QEMU which ports the TDX code before it's merged
upstream. Now TDX is upstreamed, it works with upstream compat property
and I think future new compat property won'
On 7/2/2025 11:10 PM, Xiaoyao Li wrote:
On 7/2/2025 10:16 PM, Xiaoyao Li wrote:
On 5/23/2025 11:44 PM, Kirill Martynov wrote:
Certain error conditions can trigger x86_cpu_dump_state() to output
CPU state
debug information e.g. KVM emulation failure due to misbehaving guest.
However, if the
On 7/2/2025 10:16 PM, Xiaoyao Li wrote:
On 5/23/2025 11:44 PM, Kirill Martynov wrote:
Certain error conditions can trigger x86_cpu_dump_state() to output
CPU state
debug information e.g. KVM emulation failure due to misbehaving guest.
However, if the CPU is in System Management Mode (SMM) when
On 5/23/2025 11:44 PM, Kirill Martynov wrote:
Certain error conditions can trigger x86_cpu_dump_state() to output CPU state
debug information e.g. KVM emulation failure due to misbehaving guest.
However, if the CPU is in System Management Mode (SMM) when the assertion
in cpu_asidx_from_attrs fail
On 7/2/2025 8:12 PM, Paolo Bonzini wrote:
Il mer 2 lug 2025, 07:42 Xiaoyao Li ha scritto:
Back to Paolo's example of "a compat property will be set on a device
*after* the class's post_init callback has run". I think the behavior of
compat property is applied after t
On 7/2/2025 3:56 PM, Zhao Liu wrote:
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 0d35e95430fe..bf290262cbfe 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -9044,6 +9044,12 @@ static void x86_cpu_post_initfn(Object *obj)
X86_CONFIDENTIAL_GUEST(current_machine
On 7/2/2025 1:01 PM, Zhao Liu wrote:
Thanks Igor for looking here and thanks Konrad's explanation.
On 7/1/2025 6:26 PM, Zhao Liu wrote:
unless it was explicitly requested by the user.
But this could still break Windows, just like issue #3001, which enables
arch-capabilities for EPYC-Genoa. Th
On 7/2/2025 3:47 AM, Konrad Rzeszutek Wilk wrote:
On Tue, Jul 01, 2025 at 05:47:06PM +0800, Xiaoyao Li wrote:
On 7/1/2025 5:22 PM, Alexandre Chartre wrote:
On 7/1/25 10:23, Xiaoyao Li wrote:
On 6/30/2025 9:30 PM, Alexandre Chartre wrote:
KVM emulates the ARCH_CAPABILITIES on x86 for both
On 7/1/2025 8:12 PM, Alexandre Chartre wrote:
On 7/1/25 13:12, Xiaoyao Li wrote:
On 7/1/2025 6:26 PM, Zhao Liu wrote:
unless it was explicitly requested by the user.
But this could still break Windows, just like issue #3001, which enables
arch-capabilities for EPYC-Genoa. This fact shows
On 7/1/2025 6:26 PM, Zhao Liu wrote:
unless it was explicitly requested by the user.
But this could still break Windows, just like issue #3001, which enables
arch-capabilities for EPYC-Genoa. This fact shows that even explicitly
turning on arch-capabilities in AMD Guest and utilizing KVM's emula
;t stop me from trying to associate it with
"host" cpu type.
Anyway, if most people leans towards separating the files, I'm also OK.
Bye,
Claudio
On 7/1/25 09:57, Xiaoyao Li wrote:
The name of host_cpu_instance_init is really confusing. It misleads
people to think it as the
On 7/1/2025 5:22 PM, Alexandre Chartre wrote:
On 7/1/25 10:23, Xiaoyao Li wrote:
On 6/30/2025 9:30 PM, Alexandre Chartre wrote:
KVM emulates the ARCH_CAPABILITIES on x86 for both Intel and AMD
cpus, although the IA32_ARCH_CAPABILITIES MSR is an Intel-specific
MSR and it makes no sense to
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