On Mon, Oct 07, 2024 at 08:45:07AM -0500, Michael Galaxy wrote:
> Hi,
>
> On 10/7/24 03:47, Yu Zhang wrote:
> > !---|
> >This Message Is From an External Sender
> >This message came from outside your organization.
> > |---
On Wed, Jun 05, 2024 at 10:00:24AM +, Gonglei (Arei) wrote:
>
>
> > -Original Message-
> > From: Michael S. Tsirkin [mailto:m...@redhat.com]
> > Sent: Wednesday, June 5, 2024 3:57 PM
> > To: Gonglei (Arei)
> > Cc: qemu-devel@nongnu.org; pet...@redhat.com; yu.zh...@ionos.com;
> > mgal
From: Leon Schuermann
When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the PMP
configuration lock bits must not apply. While this behavior is
implemented for the pmpcfgX CSRs, this bit is not respected for
changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR
writes
mmu_idx, 0);
+// Nonfaulting page-table read:
+cc->tcg_ops->tlb_fill(cs, addr, 0, MMU_INST_FETCH, mmu_idx, true,
+ 0);
index = tlb_index(env, mmu_idx, addr);
entry = tlb_entry(env, mmu_idx, addr);
However, given this touches the generic TCG implementation, I cannot
judge whether this is correct or has any unintended side effects for
other targets. If this is correct, I'd be happy to send a proper patch.
-Leon
From: Leon Schuermann
This commit fixes PMP address access checks with non page-aligned PMP
regions on harts with MPU enabled. Without this change, the presence
of an MPU in the virtual CPU model would influence the PMP address
check behavior when an access size was unknown (`size == 0
On Wed, Sep 22, 2021 at 09:37:37PM +0800, 魏俊吉 wrote:
> On Wed, Sep 22, 2021 at 9:06 PM Leon Romanovsky wrote:
> >
> > On Wed, Sep 22, 2021 at 08:08:44PM +0800, Junji Wei wrote:
> > > > On Sep 15, 2021, at 9:43 PM, Jason Gunthorpe wrote:
> >
> > <...>
On Wed, Sep 22, 2021 at 08:08:44PM +0800, Junji Wei wrote:
> > On Sep 15, 2021, at 9:43 PM, Jason Gunthorpe wrote:
<...>
> >> 4. The FRMR api need to set key of MR through IB_WR_REG_MR.
> >> But it is impossible to change a key of mr using uverbs.
> >
> > FRMR is more like memory windows in u
On Fri, Apr 19, 2019 at 01:16:06PM +0200, Hannes Reinecke wrote:
> On 4/15/19 12:35 PM, Yuval Shaia wrote:
> > On Thu, Apr 11, 2019 at 07:02:15PM +0200, Cornelia Huck wrote:
> > > On Thu, 11 Apr 2019 14:01:54 +0300
> > > Yuval Shaia wrote:
> > >
> > > > Data center backends use more and more RDMA
/0x5579e7b6d730: shared -> disconnected
** Changed in: qemu
Assignee: (unassigned) => leon (liayan)
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1686390
Title:
vnc server closed socke
** Description changed:
This is a rewrite for https://bugs.launchpad.net/qemu/+bug/1670377
QEMU 2.6 or later
- tigervncviwer 1.6
+ tigervncviwer 1.6
Once get into grub boot interface(choose boot os, or recovery mode),
- keep pressing arrow down button for couple times, qemu will clos
Public bug reported:
This is a rewrite for https://bugs.launchpad.net/qemu/+bug/1670377
QEMU 2.6 or later
tigervncviwer 1.6
Once get into grub boot interface(choose boot os, or recovery mode),
keep pressing arrow down button for couple times, qemu will close the
connection, vnc used zrle mode.
On Tue, Apr 04, 2017 at 04:38:40PM +0300, Marcel Apfelbaum wrote:
> On 04/03/2017 09:23 AM, Leon Romanovsky wrote:
> > On Fri, Mar 31, 2017 at 06:45:43PM +0300, Marcel Apfelbaum wrote:
> > > On 03/30/2017 11:28 PM, Doug Ledford wrote:
> > > > On 3/30/17 9:13 AM, Leon
On Thu, Mar 30, 2017 at 03:28:21PM -0500, Doug Ledford wrote:
> On 3/30/17 9:13 AM, Leon Romanovsky wrote:
> > On Thu, Mar 30, 2017 at 02:12:21PM +0300, Marcel Apfelbaum wrote:
> > > From: Yuval Shaia
> > >
> > > Hi,
> > >
> > > General d
On Fri, Mar 31, 2017 at 06:45:43PM +0300, Marcel Apfelbaum wrote:
> On 03/30/2017 11:28 PM, Doug Ledford wrote:
> > On 3/30/17 9:13 AM, Leon Romanovsky wrote:
> > > On Thu, Mar 30, 2017 at 02:12:21PM +0300, Marcel Apfelbaum wrote:
> > > > From: Yu
On Thu, Mar 30, 2017 at 02:12:21PM +0300, Marcel Apfelbaum wrote:
> From: Yuval Shaia
>
> Hi,
>
> General description
> ===
> This is a very early RFC of a new RoCE emulated device
> that enables guests to use the RDMA stack without having
> a real hardware in the host.
>
>
While testing mttcg I noticed that VP0 gets stuck in a loop waiting
for other VPs to come up (which never actually happens). To fix this
kick VPs while they are being powered up by Cluster Power Controller.
Signed-off-by: Leon Alrae
---
hw/misc/mips_cpc.c |1 +
1 files changed, 1 insertions
On Wed, Sep 21, 2016 at 01:16:28PM -0700, Richard Henderson wrote:
> On 09/21/2016 01:07 AM, Leon Alrae wrote:
> >+tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1);
> >+tcg_temp_free(addr);
> >+tcg_gen_movi_tl(t0, 0);
> >+tcg_gen_br(done);
&g
This patch completely rewrites conditional stores. Now we use cmpxchg and
no longer need separate implementations for user and system emulation.
Signed-off-by: Leon Alrae
Reviewed-by: Richard Henderson
---
linux-user/main.c | 58 --
target-mips/cpu.h | 4
uce CP0_LLAddr which is
the actual Coperocessor 0 LLAddr register that guest can access.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 3 ++-
target-mips/machine.c | 7 ---
target-mips/op_helper.c | 29 +
target-mips/translate.c | 4 ++--
4 files changed,
Richard's comments
Leon Alrae (2):
target-mips: compare virtual addresses in LL/SC sequence
target-mips: reimplement SC instruction and use cmpxchg
linux-user/main.c | 58 -
target-mips/cpu.h | 7 +--
target-mips/helper.c| 6 +--
target-mips/hel
patch also fixes some fcntl()-related LTP tests for Qemu
user mode for Mips.
Signed-off-by: Miodrag Dinic
Signed-off-by: Aleksandar Markovic
Reviewed-by: Laurent Vivier
Reviewed-by: Leon Alrae
Acked-by: Riku Voipio
Signed-off-by: Leon Alrae
---
linux-user/syscall_defs.h | 2 +-
1 file
arch/mips/include/uapi/asm/sockios.h#L19
for reference.
This patch also a fixes LTP test failure for test sockioctl01, for
mips, alpha, and sh4.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Reviewed-by: Laurent Vivier
Reviewed-by: Leon Alrae
Acked-by: Riku Voipio
Sig
Make use of memory barrier TCG opcode in MIPS front end.
Signed-off-by: Leon Alrae
Reviewed-by: Richard Henderson
---
target-mips/translate.c | 32 ++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
, for 64-bit Mips architectures there is no such rearrangement,
and this patch reflects it.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Reviewed-by: Laurent Vivier
Reviewed-by: Leon Alrae
Acked-by: Riku Voipio
Signed-off-by: Leon Alrae
---
linux-user/syscall.c | 2 +-
1
cept4(3,1996486000,1996486016,128,0,0) = 5
Such output may be further improved by providing strace-related functions
that handle only particular syscalls, but this is beyond the scope of
this patch.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Laurent Vivier
Acked-by: Riku Voipio
Signed-off-by: Leon
Reviewed-by: Leon Alrae
Acked-by: Riku Voipio
Signed-off-by: Leon Alrae
---
linux-user/syscall_defs.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 925feda..9fdbe86 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user
these syscalls are not yet supported in Qemu, but once they are
supported, they will need correct EDQUOT handling.)
Signed-off-by: Aleksandar Markovic
Reviewed-by: Laurent Vivier
Acked-by: Riku Voipio
Signed-off-by: Leon Alrae
---
linux-user/mips/target_syscall.h | 2 ++
linux-user/mips64
executed in Qemu user mode for any Mips platform.
Signed-off-by: Miodrag Dinic
Signed-off-by: Aleksandar Markovic
Reviewed-by: Peter Maydell
Reviewed-by: Laurent Vivier
Reviewed-by: Leon Alrae
Acked-by: Riku Voipio
Signed-off-by: Leon Alrae
---
linux-user/mips/target_structs.h | 16
From: André Draszik
Define a new CPU definition supporting 24KEc cores, similar to
the existing 24Kc, but with added support for DSP instructions
and MIPS16e (and without FPU).
Signed-off-by: André Draszik
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 22
Hi,
Here's my queue with the MIPS patches I've accumulated so far.
Thanks,
Leon
Cc: Peter Maydell
Cc: Aurelien Jarno
The following changes since commit 430da7a81d356e368ccd88dcca60f38da9aa5b9a:
Merge remote-tracking branch 'remotes/riku/tags/pull-linux-user-20160915'
Yongbok Kim takes over the target-mips maintenance from me.
Signed-off-by: Leon Alrae
---
Hi,
September is my last month in ImgTec, and therefore soon I won't be able to
look after target-mips code. I would like to nominate Yongbok Kim as the new
co-maintainer. Yongbok contributed qu
On Wed, Sep 21, 2016 at 07:12:20PM +, Riku Voipio wrote:
> On Wed, Sep 21, 2016 at 02:16:54PM +0100, Leon Alrae wrote:
> > On Mon, Sep 19, 2016 at 01:44:37PM +0200, Aleksandar Markovic wrote:
> > > From: Aleksandar Markovic
> > >
> > > v6->v7:
>
tructs.h | 16 ++
> linux-user/mips/target_syscall.h | 2 +
> linux-user/mips64/target_syscall.h | 2 +
> linux-user/strace.list | 114
> +
> linux-user/syscall.c | 3 +-
> linux-user/syscall_defs.h | 12 +++-
> 6 files changed, 147 insertions(+), 2 deletions(-)
Applied to target-mips queue, thanks.
Leon
and that tag is not there.
Thanks,
Leon
uce CP0_LLAddr which is
the actual Coperocessor 0 LLAddr register that guest can access.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 3 ++-
target-mips/machine.c | 7 ---
target-mips/op_helper.c | 29 +
target-mips/translate.c | 4 ++--
4 files changed,
This patch completely rewrites conditional stores. Now we use cmpxchg and
no longer need separate implementations for user and system emulation.
Signed-off-by: Leon Alrae
---
linux-user/main.c | 58 --
target-mips/cpu.h | 4 --
target-mips/helper.c
this is a missing piece in atomic helpers rather
than a problem in the code gen.
v2:
* improved and simplified SC implementation according to Richard's comments
Leon Alrae (2):
target-mips: compare virtual addresses in LL/SC sequence
target-mips: reimplement SC instruction and use cmpxc
On Fri, Sep 16, 2016 at 09:48:51AM -0700, Richard Henderson wrote:
> On 09/15/2016 01:44 AM, Leon Alrae wrote:
> > /* Store conditional */
> >+static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset,
> >+int size)
> > {
have incorrect size. This should be abi_long.
> +#endif
> int l_pid;
> +#if defined(TARGET_MIPS)
> +target_long pad[4];
Same.
Otherwise the series looks good to me.
Thanks,
Leon
> +#endif
> };
>
> struct target_flock64 {
> --
> 2.9.3
>
uce CP0_LLAddr which is
the actual Coperocessor 0 LLAddr register that guest can access.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 3 ++-
target-mips/machine.c | 7 ---
target-mips/op_helper.c | 29 +
target-mips/translate.c | 4 ++--
4 files changed,
This patch completely rewrites conditional stores. Now we use cmpxchg and
no longer need separate implementations for user and system emulation.
Signed-off-by: Leon Alrae
---
linux-user/main.c | 58 -
target-mips/cpu.h | 4 --
target-mips/helper.c| 6
this is a missing piece in atomic helpers rather
than a problem in the code gen.
Leon Alrae (2):
target-mips: compare virtual addresses in LL/SC sequence
target-mips: reimplement SC instruction and use cmpxchg
linux-user/main.c | 58 -
target-mips/cpu.h
On Mon, Sep 12, 2016 at 09:13:10AM -0700, Richard Henderson wrote:
> On 09/12/2016 12:59 AM, Leon Alrae wrote:
> >On Fri, Sep 09, 2016 at 09:26:29AM -0700, Richard Henderson wrote:
> >>On 09/09/2016 07:46 AM, Leon Alrae wrote:
> >>>Wouldn't it be useful if tcg.
On Fri, Sep 09, 2016 at 09:26:29AM -0700, Richard Henderson wrote:
> On 09/09/2016 07:46 AM, Leon Alrae wrote:
> >Wouldn't it be useful if tcg.h provided also aliases for _le/_be atomic
> >helpers (equivalent to helper_ret_X_mmu) so that in target-* code we wouldn't
ldn't
need to care about the endianness (specifically I'm thinking about SC in MIPS
where I need to select between helper_atomic_cmpxchgl_le_mmu() and
helper_atomic_cmpxchgl_be_mmu()).
Thanks,
Leon
> +#define GEN_ATOMIC_HELPER(NAME, OP, NEW)\
> +static void * const table_##NAME[16] = {\
> +[MO_8] = gen_helper_atomic_##NAME##b, \
> +[MO_16 | MO_LE] = gen_helper_atomic_##NAME##w_le,
On Sat, Sep 03, 2016 at 09:39:33PM +0100, Richard Henderson wrote:
> Allows Int128 to be used more generally, rather than having to
> begin with 64-bit inputs and accumulate.
>
> Signed-off-by: Richard Henderson
> ---
> include/qemu/int128.h | 20 +++-
> 1 file changed, 15 insert
NC exist also in earlier revisions of
MIPS architecture; therefore this can be tested for example on mips32r2.
According to manuals the support is optional, and if given CPU doesn't
implement lightweight SYNCs (i.e. with stype != 0) then they are supposed
to behave in the same way as SYNC 0. (which also means I simplified that here
and always interpret the stype to take advantage of weaker ordering barriers).
Thanks,
Leon
tch you need to add also your Signed-off-by:
line here (similarly in other patches in the series).
Thanks,
Leon
> ---
> linux-user/syscall_defs.h |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
> index
On Thu, Sep 08, 2016 at 11:46:38AM +0100, Paul Burton wrote:
> On 08/09/16 09:57, Leon Alrae wrote:
> > On Fri, Aug 19, 2016 at 08:40:32PM +0100, Paul Burton wrote:
> >> On 19/08/16 20:25, no-re...@patchew.org wrote:
> >>> Hi,
> >>>
> >>> Yo
Make use of memory barrier TCG opcode in MIPS front end.
Signed-off-by: Leon Alrae
---
v2:
* generate weaker barriers according to stype
---
target-mips/translate.c | 32 ++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate.c b
27;m open to
> suggestions about how to handle that...
Looks like 1.4.2 has appeared recently and it contains above commit.
One way would be just to bump our minimal dtc version requirement from
1.4.0 to 1.4.2 (and update qemu's dtc submodule as well)...
Thanks,
Leon
>
> Thanks,
Make use of memory barrier TCG opcode in MIPS front end.
Signed-off-by: Leon Alrae
---
This patch complements the following series:
https://lists.nongnu.org/archive/html/qemu-devel/2016-07/msg03283.html
---
target-mips/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
ps/cpu.h | 1 +
> target-mips/translate.c | 10 ++
> 2 files changed, 11 insertions(+)
Reviewed-by: Leon Alrae
ons(+), 25 deletions(-)
Reviewed-by: Leon Alrae
on
> ---
> hw/timer/mips_gictimer.c | 5 +
> include/hw/timer/mips_gictimer.h | 1 +
> 2 files changed, 6 insertions(+)
Reviewed-by: Leon Alrae
break;
> diff --git a/include/hw/misc/mips_cmgcr.h b/include/hw/misc/mips_cmgcr.h
> index a209d91..31bda6a 100644
> --- a/include/hw/misc/mips_cmgcr.h
> +++ b/include/hw/misc/mips_cmgcr.h
> @@ -41,6 +41,9 @@
> #define GCR_L2_CONFIG_BYPASS_SHF20
> #define GCR_L2_CONFIG_BYPASS_MSK((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF)
>
> +/* GCR_BASE register fields */
> +#define GCR_BASE_GCRBASE_MSK 0x8000ULL;
Unnecessary semicolon?
Otherwise
Reviewed-by: Leon Alrae
While implementing TLB invalidation feature we forgot to modify
part of code responsible for updating EntryHi during TLB exception.
Consequently EntryHi.EHINV is unexpectedly cleared on the exception.
Signed-off-by: Leon Alrae
---
target-mips/helper.c | 1 +
1 file changed, 1 insertion(+)
diff
Hi,
Just a couple of bug fixes for rc1.
Thanks,
Leon
Cc: Peter Maydell
Cc: Aurelien Jarno
The following changes since commit 21a21b853a1bb606358af61e738abfb9aecbd720:
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into
staging (2016-07-27 18:18:21 +
wind up printing a continuous stream of the letter E.
Signed-off-by: Paul Burton
Cc: Aurelien Jarno
Cc: Leon Alrae
Reviewed-by: Aurelien Jarno
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
While implementing TLB invalidation feature we forgot to modify
part of code responsible for updating EntryHi during TLB exception.
Consequently EntryHi.EHINV is unexpectedly cleared on the exception.
Signed-off-by: Leon Alrae
---
target-mips/helper.c |1 +
1 files changed, 1 insertions
get-mips/op_helper.c | 18 +-
> translate-all.c | 1 +
> 6 files changed, 24 insertions(+), 48 deletions(-)
Looks good to me:
Reviewed-by: Leon Alrae
Thanks,
Leon
mips/translate_init.c | 22 ++
> 1 file changed, 22 insertions(+)
Thanks for the patch. We are currently in hard feature freeze and we are
merging bug-fixes only, so I applied it to the post-v2.7 target-mips queue.
Leon
t; indicating the configuration mismatch but QEMU would previously
> incorrectly jump & wind up printing a continuous stream of the letter E.
>
> Signed-off-by: Paul Burton
> Cc: Aurelien Jarno
> Cc: Leon Alrae
> ---
> hw/mips/mips_malta.c | 2 +-
> 1 file changed,
On Thu, Jul 14, 2016 at 04:43:42PM +0300, Marcel Apfelbaum wrote:
> Delay the host-bridge 'realization' until the
> PCI root bus is attached.
>
> Signed-off-by: Marcel Apfelbaum
> ---
> hw/mips/gt64xxx_pci.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-
From: Paul Burton
Signed-off-by: Paul Burton
Signed-off-by: James Hogan
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 2 ++
target-mips/helper.c| 10 +-
target-mips/op_helper.c | 27 +++
target-mips/translate.c | 1 +
4 files changed, 23
From: Paul Burton
ASID currently has uint8_t type which is too small since some processors
support more than 8 bits ASID. Therefore change its type to uint16_t.
Signed-off-by: Paul Burton
Signed-off-by: James Hogan
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 2 +-
target-mips
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c43bdb7..39ed5c4 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -685,7
will start execution.
Signed-off-by: Leon Alrae
---
hw/misc/mips_cmgcr.c | 54 +++-
include/hw/misc/mips_cmgcr.h | 18 +++
2 files changed, 71 insertions(+), 1 deletion(-)
diff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_cmgcr.c
index e6cf17
sharing
global settings and registers such as GIC_SH_CONFIG.COUTNSTOP and
GIC_SH_COUNTER.
MIPS GIC Interval Timer does support upto 64 bits of Count register but
in this implementation it is limited to 32 bits only.
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
hw/timer/Makefile.objs
internal data is converted back into the
original format as the specification.
Limitations:
Level triggering only
GIC CounterHi not implemented (Countbits = 32bits)
DINT not implemented
Local WatchDog, Fast Debug Channel, Perf Counter not implemented
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
Replace hardcoded 0xbfc0 with exception_base which is initialized with
this default address so there is no functional change here.
However, it is now exposed and consequently it will be possible to modify
it from outside of the CPU.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 2
From: Paul Burton
The read-only Config4.AE bit set denotes extended 10 bits ASID.
Signed-off-by: Paul Burton
Signed-off-by: James Hogan
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 1 +
target-mips/translate.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a
Hi,
This pull request adds MIPS CPS features needed to boot MIPSr6 SMP Linux on
multiple VPs, renames MIPS64R6-generic to I6400 and adds 10-bit ASID support.
Thanks,
Leon
Cc: Peter Maydell
Cc: Aurelien Jarno
The following changes since commit e2c8f9e44e07d8210049abaa6042ec3c956f1dd4
Add GIC to CPS and expose its interrupt pins instead of CPU's.
Signed-off-by: Leon Alrae
---
hw/mips/cps.c| 25 ++---
hw/mips/mips_malta.c | 4 +---
hw/misc/mips_cmgcr.c | 33 +
include/hw/mips/
MIPS64R6-generic gradually gets closer to I6400 CPU, feature-wise. Rename
it to make it clear which MIPS processor it is supposed to emulate.
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a
CPU_INTERRUPT_HALT to halt a VP.
Signed-off-by: Leon Alrae
---
hw/misc/mips_cpc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c
index e6a35dd..6d34574 100644
--- a/hw/misc/mips_cpc.c
+++ b/hw/misc/mips_cpc.c
@@ -37,7 +37,7 @@ static void
in tcg_cpu_exec (cpu=0x78939700) at
/user/lea/dev/qemu/cpus.c:1541
#30 0x7796fa52 in tcg_exec_all () at /user/lea/dev/qemu/cpus.c:1574
#31 0x7796eb15 in qemu_tcg_cpu_thread_fn (arg=0x78939700) at
/user/lea/dev/qemu/cpus.c:1171
#32 0x730ce9d1 in start_thread () from /
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c43bdb7..39ed5c4 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -685,7
From: Paul Burton
Signed-off-by: Paul Burton
Signed-off-by: James Hogan
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 2 ++
target-mips/helper.c| 10 +-
target-mips/op_helper.c | 27 +++
target-mips/translate.c | 1 +
4 files changed, 23
From: Paul Burton
ASID currently has uint8_t type which is too small since some processors
support more than 8 bits ASID. Therefore change its type to uint16_t.
Signed-off-by: Paul Burton
Signed-off-by: James Hogan
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 2 +-
target-mips
series is based on the patch adding I6400 CPU:
https://lists.gnu.org/archive/html/qemu-devel/2016-06/msg07604.html
Thanks,
Leon
Leon Alrae (1):
target-mips: enable 10-bit ASIDs in I6400 CPU
Paul Burton (3):
target-mips: add ASID mask field and replace magic values
target-mips: change ASID
From: Paul Burton
The read-only Config4.AE bit set denotes extended 10 bits ASID.
Signed-off-by: Paul Burton
Signed-off-by: James Hogan
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 1 +
target-mips/translate.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a
MIPS64R6-generic gradually gets closer to I6400 CPU, feature-wise. Rename
it to make it clear which MIPS processor it is supposed to emulate.
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a
ot needed.
[1] "IEEE Standard for Floating-Point Arithmetic",
IEEE Computer Society, August 29, 2008.
Signed-off-by: Thomas Schwinge
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Aleksandar Markovic
Tested-by: Bastian Koppelmann
Reviewed-by: Leon Alrae
Tested-by: Leon Alr
anual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015
Signed-off-by: Thomas Schwinge
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Aleksandar Markovic
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 26 ++
1 file c
From: Aleksandar Markovic
Add preprocessor definition of FCR31's FS bit, and update related
code for setting this bit.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
propagate NaNs.
* FCLASS.D ans FCLASS.S will now correcty detect NaN flavors.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-mips/translate_init.c b
The MIPS32 SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016
Signed-off-by: Aleksandar Markovic
Reviewed-by: Leon Alrae
Reviewed-by: Peter Maydell
[leon.al...@imgtec.com:
* reworded the subject of the patch
* swapped if/else code blocks
From: Aleksandar Markovic
Missing values EF_MIPS_FP64 and EF_MIPS_NAN2008 added.
Signed-off-by: Thomas Schwinge
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Aleksandar Markovic
Reviewed-by: Leon Alrae
Reviewed-by: Peter Maydell
Signed-off-by: Leon Alrae
---
include/elf.h | 2 ++
1
after
appropriate SoftFloat library function is called.
Related MSA instructions FTRUNC_S and FTINT_S already handle well
all cases, in the fashion similar to the code from this patch.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Leon Alrae
[leon.al...@imgtec.com:
* removed a statement from the
tables for Mips, in relation to the
bit EF_MIPS_NAN2008 from ELF header, that is in turn related to
reading and writing to FCR31.
- Modify gdb behavior in relation to FCR31.
Signed-off-by: Thomas Schwinge
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Aleksandar Markovic
Reviewed-by: Leon Al
debug and maintain.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Peter Maydell
Signed-off-by: Leon Alrae
---
fpu/softfloat-specialize.h | 57 +++---
1 file changed, 28 insertions(+), 29 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat
chitecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016
Signed-off-by: Aleksandar Markovic
Reviewed-by: Leon Alrae
Reviewed-by: Peter Maydell
Signed-off-by: Leon Alrae
---
fpu/softfloat-specialize.h | 12
1 file changed, 12 insertions(+)
diff
Hi,
This pull request contains patches from Aleksandar which unlock
the IEEE 754-2008 support for MIPS.
Thanks,
Leon
Cc: Peter Maydell
Cc: Aurelien Jarno
The following changes since commit c7288767523f6510cf557707d3eb5e78e519b90d:
Merge remote-tracking branch 'remotes/dgibson/tags/pp
with files located in directory target-mips only.
>
> Hi. I've reviewed the patches in Part 1, and I'm happy with them
> apart from a few trivial things. I'm not going to look at Part 2
> since it's pretty MIPS specific.
>
> I'm assuming that Leon will
the MIPS target was added
>to QEMU).
I've just done another round of review and as far as I can tell these
patches don't modify the legacy-NaN MIPS behaviour. I believe Aleksandar
was referring to new functionality (i.e. 2008 NaN) only.
Regards,
Leon
>
> 2. A new feature
| 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Leon Alrae
t-mips/cpu.h | 5 +
> target-mips/helper.h | 4 +-
> target-mips/msa_helper.c | 88 +++
> target-mips/op_helper.c | 17 +-
> target-mips/translate.c | 5 +-
> target-mips/translate_init.c | 2 +
> target-ppc/fpu_helper.c |
t; target-mips/gdbstub.c| 8 +++-
> target-mips/op_helper.c | 14 +++---
> target-mips/translate.c | 5 ++---
> target-mips/translate_init.c | 26 ++
> 6 files changed, 56 insertions(+), 19 deletions(-)
Reviewed-by: Leon Alrae
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