ate
separate SoC models and machine definitions for each one? Or can we
treat AST27x0 as a superset of AST2700, AST2750, AST2720, and
any future models?
Thanks,
Troy Lee
> Since we started separating the SoCs :
>
>hw/arm/aspeed_ast10x0.c
>hw/arm/aspeed_ast2400.c
>hw
Map the CA35 memory region as a subregion of system_memory to ensure
a valid FlatView. This prevents failures in APIs that rely on the
global memory view, such as rom_check_and_register_reset().
Signed-off-by: Steven Lee
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast27x0-fc.c | 1 +
1
This patch adds network support to the ast2700fc machine by initializing
the NIC device in the ca35.
Signed-off-by: Steven Lee
---
hw/arm/aspeed_ast27x0-fc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 125a3ade40
a safeguard.
Signed-off-by: Steven Lee
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast27x0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 1974a25766..bb61c30cf4 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw
The ast2700fc machine is now covered in the dedicated ast2700-evb
section. Listing it in the general Aspeed board family list is
redundant.
Signed-off-by: Steven Lee
Reviewed-by: Cédric Le Goater
---
docs/system/arm/aspeed.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
e for the first patch to:
"hw/arm/aspeed_ast2700-fc: Add network support".
Steven Lee (6):
hw/arm/aspeed_ast2700-fc: Add network support
hw/arm/aspeed_ast2700-fc: Reduce ca35 ram size to align with ast2700a1
hw/arm/aspeed_ast27x0: Fix unimplemented region overlap with vbootrom
hw/ar
Reduce ca35 ram size from 2GiB to 1GiB to align with ast2700a1-evb,
where the ram-container is defined as 1GiB in its class.
Signed-off-by: Steven Lee
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast27x0-fc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm
Add the BMC memory region as a subregion of system_memory so that
modules relying on system memory can operate correctly.
Signed-off-by: Steven Lee
Reviewed-by: Cédric Le Goater
---
hw/arm/fby35.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Friday, May 23, 2025 4:09 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc:
a safeguard.
Signed-off-by: Steven Lee
---
hw/arm/aspeed_ast27x0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 1974a25766..bb61c30cf4 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -23,14
Map the CA35 memory region as a subregion of system_memory to ensure
a valid FlatView. This prevents failures in APIs that rely on the
global memory view, such as rom_check_and_register_reset().
Signed-off-by: Steven Lee
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast27x0-fc.c | 1 +
1
Add the BMC memory region as a subregion of system_memory so that
modules relying on system memory can operate correctly.
Signed-off-by: Steven Lee
Reviewed-by: Cédric Le Goater
---
hw/arm/fby35.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index
c configuration in ast2700fc's ca35 init function.
Signed-off-by: Steven Lee
---
hw/arm/aspeed_ast27x0-fc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 125a3ade40..7bf4f2a52d 100644
--- a/hw/arm/aspeed_ast27
Reduce ca35 ram size from 2GiB to 1GiB to align with ast2700a1-evb,
where the ram-container is defined as 1GiB in its class.
Signed-off-by: Steven Lee
---
hw/arm/aspeed_ast27x0-fc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm
The ast2700fc machine is now covered in the dedicated ast2700-evb
section. Listing it in the general Aspeed board family list is
redundant.
Signed-off-by: Steven Lee
Reviewed-by: Cédric Le Goater
---
docs/system/arm/aspeed.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
message for "Fix unimplemented region
overlap with VBootROM".
v4:
- Split the first patch "Fix null pointer dereference" into two patches.
- Remove the patch "hw/arm/aspeed_ast27x0: Fix unimplemented
region overlap with vbootrom".
Steven Lee (6):
hw/arm/aspeed_as
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Thursday, May 22, 2025 3:52 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc:
Hi reviewers,
Please ignore this patch - I mistakenly sent two versions of patch 2/5.
The correct one is titled:
[PATCH v3 2/5] hw/arm/aspeed_ast27x0: Fix unimplemented region overlap with
VBootROM
Sorry for the confusion.
Regards,
Steven
> -Original Message-
> From: Stev
message for "Fix unimplemented region
overlap with VBootROM".
Steven Lee (5):
hw/arm/aspeed_ast2700-fc: Fix null pointer dereference in ca35 init
hw/arm/aspeed_ast27x0: Fix unimplemented region overlap with vbootrom
hw/arm/aspeed_ast27x0-fc: Map ca35 memory into system memory
e ca35 ram size from 2GiB to 1GiB to align with ast2700a1-evb,
where the ram-container is defined as 1GiB in its class.
- Add nic configuration in ast2700fc's ca35 init function.
Signed-off-by: Steven Lee
---
hw/arm/aspeed_ast27x0-fc.c | 9 -
1 file changed, 8 insertions(+), 1 delet
Map the CA35 memory region as a subregion of system_memory to ensure
a valid FlatView. This prevents failures in APIs that rely on the
global memory view, such as rom_check_and_register_reset().
Signed-off-by: Steven Lee
---
hw/arm/aspeed_ast27x0-fc.c | 1 +
1 file changed, 1 insertion(+)
diff
a safeguard.
Signed-off-by: Steven Lee
---
hw/arm/aspeed_ast27x0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 1974a25766..bb61c30cf4 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -23,14
The iomem region at 0x is unused and overlaps with VBootROM.
Removing it avoids incorrect memory layout.
Signed-off-by: Steven Lee
---
hw/arm/aspeed_ast27x0.c | 8
1 file changed, 8 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 1974a25766
The ast2700fc machine is now covered in the dedicated ast2700-evb
section. Listing it in the general Aspeed board family list is
redundant.
Signed-off-by: Steven Lee
Reviewed-by: Cédric Le Goater
---
docs/system/arm/aspeed.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
Add the BMC memory region as a subregion of system_memory so that
modules relying on system memory can operate correctly.
Signed-off-by: Steven Lee
Reviewed-by: Cédric Le Goater
---
hw/arm/fby35.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index
Hi Cédric,
> -Original Message-
> From: Steven Lee
> Sent: Thursday, May 15, 2025 1:06 PM
> To: Cédric Le Goater ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc:
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Wednesday, May 14, 2025 11:32 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc:
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Wednesday, May 14, 2025 9:28 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc:
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Wednesday, May 14, 2025 9:28 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc:
e ca35 ram size from 2GiB to 1GiB to align with ast2700a1-evb,
where the ram-container is defined as 1GiB in its class.
- Add nic configuration in ast2700fc's ca35 init function.
Signed-off-by: Steven Lee
---
hw/arm/aspeed_ast27x0-fc.c | 15 +--
1 file changed, 13 insert
The ast2700fc machine is now covered in the dedicated ast2700-evb
section. Listing it in the general Aspeed board family list is
redundant.
Signed-off-by: Steven Lee
Reviewed-by: Cédric Le Goater
---
docs/system/arm/aspeed.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
Attach CA35 memory to system_memory to ensure a valid FlatView.
Without this, dma_memory_write() used by ftgmac fail silently,
causing dhcp to break on ast2700fc, as flatview_write() returns
an error when system_memory is empty.
Signed-off-by: Steven Lee
---
hw/arm/aspeed_ast27x0-fc.c | 1 +
1
Add the BMC memory region as a subregion of system_memory so that
modules relying on system memory can operate correctly.
Signed-off-by: Steven Lee
---
hw/arm/fby35.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index e123fa69e1..c14fc2efe9 100644
--- a/hw
in the fby35 machine,
which had a similar issue (unmapped system_memory).
- Removed Change-Id tag from commit messages
Steven Lee (5):
hw/arm/aspeed_ast2700-fc: Fix null pointer dereference in ca35 init
hw/arm/aspeed_ast27x0: Fix unimplemented region overlap with vbootrom
hw/arm/aspeed_ast27x0-fc:
reserve space for VBootROM at 0x0.
Signed-off-by: Steven Lee
---
hw/arm/aspeed_ast27x0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 1974a25766..bb61c30cf4 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, May 12, 2025 4:09 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc:
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, May 12, 2025 3:37 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc:
Hi Cédric, Peter,
> -Original Message-
> From: Peter Maydell
> Sent: Friday, May 9, 2025 11:28 PM
> To: Cédric Le Goater
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Steven Lee
>
> Subject: Re: [PULL 22/23] tests/function/aspeed: Add functional test for
>
0, 8);
+ssi_transfer(s->spi, data_l);
+s->regs[R_PSPI_DATA] = (data_h | data_l);
Peter Maydell 於 2025年5月11日 週日 下午9:58寫道：
>
> On Sun, 11 May 2025 at 14:47, Peter Maydell wrote:
> >
> > On Wed, 7 May 2025 at 10:19, Tim Lee wrote:
> > >
> >
Philippe Mathieu-Daudé 於 2025年5月8日 週四 下午2:19寫道：
>
> Hi Tim,
>
> On 8/5/25 04:15, Tim Lee wrote:
> > Fix flash device part number to `mx66l1g45g` according image-bmc run on
> > npcm8xx
> > evb board (SPIFlash...SF: Detected mx66l1g45g, total 128 MiB)
> >
>
:
qemu-system-aarch64: mx66l1g45g device '/machine/unattached/device[73]'
requires 134217728 bytes, mtd0 block backend provides 67108864 bytes
Tested:
Build passes and runs ./qemu-system-aarch64 -machine npcm845-evb normally
Signed-off-by: Tim Lee
---
Changes since v1:
- Add a stat
- Created qtest to check initialization of registers in PSPI Module
- Implemented test into Build File
Tested:
./build/tests/qtest/npcm8xx-pspi_test
Signed-off-by: Tim Lee
---
Changes since v1:
- MAINTAINERS file not need to change
- Add comment for copyright/license information
- Correct CTL
reserve space for VBootROM at 0x0.
Signed-off-by: Steven Lee
Change-Id: I1d775577816b1e93bb54c899ac3722eb6902c577
---
hw/arm/aspeed_ast27x0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 1974a25766..bb61c30cf4
The ast2700fc machine is now covered in the dedicated ast2700-evb
section. Listing it in the general Aspeed board family list is
redundant.
Signed-off-by: Steven Lee
Change-Id: Ic2784d60ce4681f38059d684f477a2962ccf8bf8
---
docs/system/arm/aspeed.rst | 2 +-
1 file changed, 1 insertion(+), 1
ry. In addition, unconfigured NICs (due to missing peers)
lead to a cascade of warnings and possibly misbehavior.
Fix by:
- Reduce ca35 ram size to 1GiB to match the ast2700a1-evb.
- Map ca35_memory into system memory
- Add nic configuration in ast2700fc's ca35 init function.
Steven Lee (3):
hw/arm/as
ry. In addition, unconfigured NICs (due to missing peers)
lead to a cascade of warnings and possibly misbehavior.
Fix by:
- Reduce ca35 ram size to 1GiB to match the ast2700a1-evb.
- Map ca35_memory into system memory
- Add nic configuration in ast2700fc's ca35 init function.
Signed-off-by: S
Hi Peter,
Thanks for your suggestion. Those changes will be included in v2.
Peter Maydell 於 2025年5月6日 週二 下午8:52寫道：
>
> On Fri, 18 Apr 2025 at 10:12, Tim Lee wrote:
> >
> > - Created qtest to check initialization of registers in PSPI Module
> > - Implemented test into B
Hi Cédric, Peter,
> -Original Message-
> From: Cédric Le Goater
> Sent: Tuesday, May 6, 2025 11:15 PM
> To: Peter Maydell
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Steven Lee
> ; Jamin Lin
> Subject: Re: [PULL 22/23] tests/function/aspeed: Add functional
// Handle writable storage
if (blk_size < fiu->flash_size) {
blk_get_perm(blk, &perm, &shared_perm);
blk_set_perm(blk, BLK_PERM_ALL, BLK_PERM_ALL, &error_abort);
blk_truncate(blk, fiu->flash_size, true, PREALLOC_MODE_OFF,
BDRV_REQ_ZERO_WRITE, &error_abort);
blk_set_perm(blk, perm, shared_perm, &error_abort);
}
}
--
Best regards,
Tim Lee
tmp/qtest-974125.qmp,id=char0 -mon
chardev=char0,mode=control -display none -audio none -machine
npcm845-evb -accel qtest
[I 0.00] OPENED
[R +0.076480] endianness
[S +0.076506] OK little
{"QMP": {"version": {"qemu": {"micro": 50, "minor": 2, "major": 9},
"package": "v9.2.0-2138-g694a7d11fc"}, "capabilities": ["oob"]}}
{"execute": "qmp_capabilities"}
{"return": {}}
[R +0.079280] writel 0xf0201002 0x5
[S +0.079288] OK
[R +0.079312] writew 0xf0201000 0x1234
[S +0.079316] OK
Wrote 0x1234 to data register
[R +0.079337] readw 0xf0201000
[S +0.079341] OK 0x1234
Read 0x1234 from data register
[I +0.079565] CLOSED
ok 3 /aarch64/npcm8xx_pspi/data
# End of npcm8xx_pspi tests
# End of aarch64 tests
--
Best regards,
Tim Lee
Introduce a new test suite for ast2700fc machine.
Rename the original test_aarch64_aspeed.py to
test_aarch64_aspeed_ast2700.py.
Signed-off-by: Steven Lee
Change-Id: I3855f55c9f6e5cca1270c179445f549f8d81f36c
---
...peed.py => test_aarch64_aspeed_ast2700.py} |
to different
ARMCPUInfo which could cause some features to not be applied correctly
in specific initial functions: "cortex_a9_initfn" and
"aarch64_a35_initfn".
Sincerely,
Tim Lee
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Friday, May 2, 2025 7:11 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc:
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Friday, May 2, 2025 7:52 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc:
Corrected the hexadecimal notation for several device addresses in the
aspeed_soc_ast2700_memmap array by changing the uppercase 'X' to
lowercase 'x'.
Signed-off-by: Steven Lee
Change-Id: I45426e18ea8e68d7ccdf9b60c4ea235c4da33cc3
Reviewed-by: Cédric Le Goater
---
hw/arm/a
0x14C5000
- PWM at 0x140C
DPMCU stands for Display Port MCU controller. LTPI is used to connect to
AST1700.
AST1700 is an I/O expander that supports the DC-SCM 2.1 LTPI protocol.
It provides AST2700 with additional GPIO, UART, I3C, and other interfaces.
Signed-off-by: Steven Lee
Change-Id
(label serial1)
char device redirected to /dev/pts/53 (label serial2)
- serial0 is the console for the four Cortex-A35 primary processors,
serial1 and serial2 are the consoles for the two Cortex-M4 coprocessors.
- Connect to the consoles using a terminal emulator.
Signed-off-by: Steven Lee
9 has 10 output pins, mapped as follows:
Bit 0 -> SSPINT 160
Bit 1 -> SSPINT 161
Bit 2 -> SSPINT 162
Bit 3 -> SSPINT 163
Bit 4 -> SSPINT 164
Signed-off-by: Steven Lee
Change-Id: I924bf1a657f1e83f9e16d6673713f4a06ecdb496
---
inc
TC
The INTCIO TSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> TSPINT 160
Bit 1 -> TSPINT 161
Bit 2 -> TSPINT 162
Bit 3 -> TSPINT 163
Bit 4 -> TSPINT 164
Signed-off-by: Steven Lee
Change-Id: I3f3aca4b90129640369cf4a92deb4b9a12df5b70
Reviewed-by:
TC
The INTCIO SSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> SSPINT 160
Bit 1 -> SSPINT 161
Bit 2 -> SSPINT 162
Bit 3 -> SSPINT 163
Bit 4 -> SSPINT 164
Signed-off-by: Steven Lee
Change-Id: Ib8cb0e264505cef48e17f173e057f3b2d1ea35c4
Reviewed-by:
Add functional test for AST2700-fc machine.
Signed-off-by: Steven Lee
Change-Id: Ieced249cf471515a33f8f5f5386a2f58d431f2f9
---
tests/functional/test_aarch64_aspeed.py | 83 +
1 file changed, 83 insertions(+)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tests
ut pins, mapped as follows:
Bit 0 -> TSPINT 160
Bit 1 -> TSPINT 161
Bit 2 -> TSPINT 162
Bit 3 -> TSPINT 163
Bit 4 -> TSPINT 164
Signed-off-by: Steven Lee
Change-Id: I69eec2b68b26ef04187b2922c5f2e584b9076c66
---
include/hw/arm
- Updated Aspeed family boards list to include `ast2700fc`.
- Added boot instructions for the `ast2700fc` machine.
- Detailed the configuration and loading of firmware for the
Cortex-A35 and Cortex-M4 processors.
Signed-off-by: Steven Lee
Change-Id: Id41312e9c7cf79bc55c6f24a87a7ad9993dc7261
the document formatting issue.
Steven Lee (9):
aspeed: ast27x0: Map unimplemented devices in SoC memory
aspeed: ast27x0: Correct hex notation for device addresses
hw/intc/aspeed: Add support for AST2700 SSP INTC
hw/intc/aspeed: Add support for AST2700 TSP INTC
hw/arm/aspeed_ast27x0-ssp
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Wednesday, April 30, 2025 5:46 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Wednesday, April 30, 2025 5:35 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Wednesday, April 30, 2025 5:31 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
Corrected the hexadecimal notation for several device addresses in the
aspeed_soc_ast2700_memmap array by changing the uppercase 'X' to
lowercase 'x'.
Signed-off-by: Steven Lee
Change-Id: I45426e18ea8e68d7ccdf9b60c4ea235c4da33cc3
Reviewed-by: Cédric Le Goater
---
hw/arm/a
9 has 10 output pins, mapped as follows:
Bit 0 -> SSPINT 160
Bit 1 -> SSPINT 161
Bit 2 -> SSPINT 162
Bit 3 -> SSPINT 163
Bit 4 -> SSPINT 164
Signed-off-by: Steven Lee
Change-Id: I924bf1a657f1e83f9e16d6673713f4a06ecdb496
---
inc
(label serial1)
char device redirected to /dev/pts/53 (label serial2)
- serial0 is the console for the four Cortex-A35 primary processors,
serial1 and serial2 are the consoles for the two Cortex-M4 coprocessors.
- Connect to the consoles using a terminal emulator.
Signed-off-by: Steven Lee
Add functional test for AST2700-fc machine.
Signed-off-by: Steven Lee
Change-Id: Ieced249cf471515a33f8f5f5386a2f58d431f2f9
---
tests/functional/test_aarch64_ast2700fc.py | 137 +
1 file changed, 137 insertions(+)
create mode 100755 tests/functional/test_aarch64_ast2700fc.py
0x14C5000
- PWM at 0x140C
DPMCU stands for Display Port MCU controller. LTPI is used to connect
to AST1700.
AST1700 is an I/O expander that supports the DC-SCM 2.1 LTPI protocol.
It provides AST2700 with additional GPIO, UART, I3C, and other
interfaces.
Signed-off-by: Steven Lee
Change-Id
TC
The INTCIO SSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> SSPINT 160
Bit 1 -> SSPINT 161
Bit 2 -> SSPINT 162
Bit 3 -> SSPINT 163
Bit 4 -> SSPINT 164
Signed-off-by: Steven Lee
Change-Id: I5329767b21c0e982d3afcb87c7d1690cc04ce2ef
Reviewed-by:
ut pins, mapped as follows:
Bit 0 -> TSPINT 160
Bit 1 -> TSPINT 161
Bit 2 -> TSPINT 162
Bit 3 -> TSPINT 163
Bit 4 -> TSPINT 164
Signed-off-by: Steven Lee
Change-Id: I69eec2b68b26ef04187b2922c5f2e584b9076c66
---
include/hw/arm
TC
The INTCIO TSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> TSPINT 160
Bit 1 -> TSPINT 161
Bit 2 -> TSPINT 162
Bit 3 -> TSPINT 163
Bit 4 -> TSPINT 164
Signed-off-by: Steven Lee
Change-Id: I9e71a8aac400c0cdbd5b78073d0ada79d12a1350
Reviewed-by:
- Updated Aspeed family boards list to include `ast2700fc`.
- Added boot instructions for the `ast2700fc` machine.
- Detailed the configuration and loading of firmware for the
Cortex-A35 and Cortex-M4 processors.
Signed-off-by: Steven Lee
Change-Id: I48d90589d29ae6bb70a172e1798f18c0c38e6e22
AST27x0 A0 TSP SoC and AST27x0 A1 TSP SoC
- Add functional tests for AST2700FC A0 and AST2700FC A1
- Add Documentation for AST2700FC
v3:
- Remove A0 SoC support and related functional tests
Steven Lee (9):
aspeed: ast27x0: Map unimplemented devices in SoC memory
aspeed: ast27x0: Correct
NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core
Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals.
Correct the `valid_cpu_types` setting to match the NPCM8XX SoC.
Signed-off-by: Tim Lee
---
hw/arm/npcm8xx_boards.c | 2 +-
1 file changed, 1 insertion(+), 1
- Created qtest to check initialization of registers in PSPI Module
- Implemented test into Build File
Tested:
./build/tests/qtest/npcm8xx-pspi_test
Signed-off-by: Tim Lee
---
MAINTAINERS | 1 +
tests/qtest/meson.build | 3 +
tests/qtest/npcm8xx_pspi-test.c
Nuvoton's PSPI is a general purpose SPI module which enables
connections to SPI-based peripheral devices. Attach it to the NPCM8XX.
Tested:
NPCM8XX PSPI driver probed successfully from dmesg log.
Signed-off-by: Tim Lee
---
hw/arm/npcm8xx.c | 11 ++-
include/hw/arm/npcm
> -Original Message-
> From: Cédric Le Goater
> Sent: Wednesday, March 26, 2025 1:34 AM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, April 7, 2025 11:18 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, April 7, 2025 11:16 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee
:
qemu-system-aarch64: mx66l1g45g device '/machine/unattached/device[73]'
requires 134217728 bytes, mtd0 block backend provides 67108864 bytes
Tested:
Build passes and runs ./qemu-system-aarch64 -machine npcm845-evb normally
Signed-off-by: Tim Lee
---
hw/arm/npcm8xx_boa
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Thursday, March 20, 2025 11:29 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
if the `eth0` ISR is not
handled.
Signed-off-by: Steven Lee
Change-Id: Ic3609eb72218dfd68be6057d78b8953b18828709
---
hw/intc/aspeed_intc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 3fd417084f..f17bf43925 100644
--- a
help to review this patch at your convenience.
Best regards,
Steven Lee
Steven Lee (1):
hw/intc/aspeed: Fix IRQ handler mask check
hw/intc/aspeed_intc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
2.43.0
> -Original Message-
> From: Cédric Le Goater
> Sent: Tuesday, March 18, 2025 8:39 PM
> To: Troy Lee ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley ;
> open list:ASPEED BMCs ; open list:All patches CC
> here
>
Commit 6de4aa8dc544 ("hw/arm/aspeed_ast27x0: Add SoC Support for AST2700
A1") extends ast2700a1 spis_num to 3, but ASPEED_SPIS_NUM defines the
maximum number of spi controller to 2, result in ehci[0] is being
overwritten in runtime.
Signed-off-by: Troy Lee
---
include/hw/arm/aspeed
, AST27x0A0 only has 2 EHCI controllers due to hw issue.
Signed-off-by: Troy Lee
---
hw/arm/aspeed_ast27x0.c | 28
include/hw/arm/aspeed_soc.h | 4 +++-
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
by: Steven Lee
Change-Id: Ifebfd7a19be0f8bcbebb20b2116f1ea353f422ab
---
hw/arm/aspeed_ast27x0-fc.c | 190 +
hw/arm/meson.build | 4 +-
2 files changed, 193 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/aspeed_ast27x0-fc.c
diff --gi
Add functional test for AST2700a1-fc machine.
Signed-off-by: Steven Lee
Change-Id: I87584164b2632c58d2e051fd92d9e280347bcf19
---
tests/functional/test_aarch64_ast2700fc.py | 38 +-
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/tests/functional
support for UART, INTC, and SCU devices
- Map unimplemented devices for IPC and SCUIO
Signed-off-by: Steven Lee
Change-Id: I8ac6e79a2739c76b802a1dfd6c7a7ef357de60a6
---
include/hw/arm/aspeed_soc.h | 12 ++
hw/arm/aspeed_ast27x0-tsp.c | 309
hw/arm/meson.build
0x14C5000
- PWM at 0x140C
DPMCU stands for Display Port MCU controller. LTPI is used to connect
to AST1700.
AST1700 is an I/O expander that supports the DC-SCM 2.1 LTPI protocol.
It provides AST2700 with additional GPIO, UART, I3C, and other
interfaces.
Signed-off-by: Steven Lee
Change-Id
support for UART, INTC, and SCU devices
- Map unimplemented devices for IPC and SCUIO
Signed-off-by: Steven Lee
Change-Id: If83e752873af393f3b71249176454399de0be40f
---
include/hw/arm/aspeed_soc.h | 14 ++
hw/arm/aspeed_ast27x0-ssp.c | 309
hw/arm/meson.build
Bit 4 -> SSPINT 164
Signed-off-by: Steven Lee
Change-Id: Ic5121dd78c5dacf1ec4b4e791cc7bf476a8b608f
---
hw/arm/aspeed_ast27x0-ssp.c | 91 +
1 file changed, 91 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 88f27
TC
The INTCIO TSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> TSPINT 160
Bit 1 -> TSPINT 161
Bit 2 -> TSPINT 162
Bit 3 -> TSPINT 163
Bit 4 -> TSPINT 164
Signed-off-by: Steven Lee
Change-Id: I9e71a8aac400c0cdbd5b78073d0ada79d12a1350
---
inclu
Introduce a new functional test for AST2700 multi-SoCs.
The test includes booting ast2700 with bmc image on
ca35 cores and booting ssp/tsp firmware on cm4 cores.
Assets for SDK and SSP/TSP images are downloaded from
AspeedTech-BMC's OpenBmc release page.
Signed-off-by: Steven Lee
Chan
Corrected the hexadecimal notation for several device addresses in the
aspeed_soc_ast2700_memmap array by changing the uppercase 'X' to
lowercase 'x'.
Signed-off-by: Steven Lee
Change-Id: I45426e18ea8e68d7ccdf9b60c4ea235c4da33cc3
---
hw/arm/aspeed_ast27x0.c | 28 +++
Bit 4 -> TSPINT 164
Signed-off-by: Steven Lee
Change-Id: Ia96cc94d10c26b77caf00dd1346565382474e937
---
hw/arm/aspeed_ast27x0-tsp.c | 91 +
1 file changed, 91 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index ed14a
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