On Tue, Jul 01, 2025 at 03:05:00PM +0200, Igor Mammedov wrote:
> On Tue, 1 Jul 2025 20:36:43 +0800
> Zhao Liu wrote:
>
> > On Tue, Jul 01, 2025 at 07:12:44PM +0800, Xiaoyao Li wrote:
> > > Date: Tue, 1 Jul 2025 19:12:44 +0800
> > > From: Xiaoyao Li
> > > Subject: Re: [PATCH] i386/cpu: ARCH_CAPAB
..snip..
> OK, back to the original question "what should the code do?"
>
> My answer is, it can behave with any of below option:
>
> - Be vendor agnostic and stick to x86 architecture. If CPUID enumerates a
> feature, then the feature is available architecturally.
Exactly. That is what we belie
On Tue, Jul 01, 2025 at 05:47:06PM +0800, Xiaoyao Li wrote:
> On 7/1/2025 5:22 PM, Alexandre Chartre wrote:
> >
> > On 7/1/25 10:23, Xiaoyao Li wrote:
> > > On 6/30/2025 9:30 PM, Alexandre Chartre wrote:
> > > > KVM emulates the ARCH_CAPABILITIES on x86 for both Intel and AMD
> > > > cpus, althoug
> -Original Message-
> From: Alistair Francis
> Sent: 16 December 2024 05:55
> To: Konrad, Frederic
> Cc: qemu-ri...@nongnu.org; pal...@dabbelt.com; alistair.fran...@wdc.com;
> bmeng...@gmail.com; liwei1...@gmail.com;
> dbarb...@ventanamicro.com; zhiwei_...@linux
itional store
>
> On 12/11/24 15:19, Frederic Konrad wrote:
> > +/*
> > + * A misaligned store trap should be triggered even if the store should
> > + * fail due to the reservation.
> > + */
> > +tcg_gen_andi_tl(tmp, src1, ~((uint64_t)0) <&l
Hi Richard,
Thanks for the comment.
> -Original Message-
> From: Richard Henderson
> Sent: 11 December 2024 22:50
> To: Konrad, Frederic ; qemu-ri...@nongnu.org
> Cc: pal...@dabbelt.com; alistair.fran...@wdc.com; bmeng...@gmail.com;
> liwei1...@gmail.com;
> dbar
rally aligned, so this fixes that
wrong behavior by raising address-misaligned exception if the address in rs1
is not naturally aligned.
Signed-off-by: Frederic Konrad
---
target/riscv/insn_trans/trans_rva.c.inc | 19 +++
1 file changed, 19 insertions(+)
diff --git a/target/ris
Now there is an option to enable misaligned accesses traps, check the alignment
during load and store for the RVI instructions. Do not generate them if the
zama16b extension is there.
Signed-off-by: Frederic Konrad
---
target/riscv/insn_trans/trans_rvi.c.inc | 7 +++
1 file changed, 7
misaligned access
happens.
Signed-off-by: Frederic Konrad
---
target/riscv/cpu.c | 5 +
target/riscv/cpu_cfg.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f219f0c3b5..1696d3db2a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
turally aligned even if
the store shouldn't happen.
Best Regards,
Fred
Frederic Konrad (3):
target/riscv: add a trap-misaligned-access property
target/riscv: generate misaligned access trap for rvi insn
target/riscv: fix the trap generation for conditional store
Hi,
> -Original Message-
> From: qemu-devel-bounces+fkonrad=amd@nongnu.org
> On Behalf Of
> Peter Maydell
> Sent: Friday, April 12, 2024 12:07 PM
> To: Alexandra Diupina
> Cc: Alistair Francis ; Edgar E. Iglesias
> ; qemu-...@nongnu.org; qemu-
> de...@nongnu.org; sdl.q...@linuxtest
Hi,
Those are various simple fixes for ZynqMP:
* 1: fixes a possible out of bound access in the SPI model.
* 2: is a trivial fix for documentation url.
* 3: is a log guest error fix for the CSU DMA.
Best Regards,
Fred
Frederic Konrad (3):
hw/ssi/xilinx_spips: fix an out of bound access
out of s->regs[addr] in xilinx_spips_write for spips and qspips.
This fixes that wrong behavior.
Reviewed-by: Luc Michel
Signed-off-by: Frederic Konrad
---
hw/ssi/xilinx_spips.c | 7 ++-
include/hw/ssi/xilinx_spips.h | 3 +++
2 files changed, 9 insertions(+), 1 deletion(-)
d
It seems that the url changed a bit, and it triggers an error. Fix the URLs so
the documentation can be reached again.
Signed-off-by: Frederic Konrad
---
hw/dma/xlnx_csu_dma.c | 2 +-
include/hw/misc/xlnx-versal-cframe-reg.h | 2 +-
include/hw/misc/xlnx-versal-cfu.h
case.
While at it remove the comment marking the SIZE register as write-only.
See:
https://docs.xilinx.com/r/en-US/ug1087-zynq-ultrascale-registers/CSUDMA_SRC_SIZE-CSUDMA-Register
Signed-off-by: Frederic Konrad
---
hw/dma/xlnx_csu_dma.c | 12
1 file changed, 8 insertions(+), 4
c:
commit 58ac482a66de09a7590f705e53fc6a3fb8a055e8
Author: Frederic Konrad
Date: Tue Jun 14 15:59:15 2016 +0100
introduce xlnx-dp
This is the implementation of the DisplayPort.
It has an aux-bus to access dpcd and edid.
This commit has the following comment in it:
+static void xlnx_dp_audio_cal
Hi,
> -Original Message-
> From: qemu-devel-bounces+fkonrad=amd@nongnu.org
> On Behalf Of
> Qiang Liu
> Sent: 09 January 2023 07:00
> To: qemu-devel@nongnu.org
> Cc: Qiang Liu ; Alistair Francis
> ; Edgar E. Iglesias ; Peter
> Maydell ; open list:Xilinx ZynqMP and...
>
> Subject:
est Regards,
Fred
-Original Message-
From: Philippe Mathieu-Daudé
Sent: 05 December 2022 09:24
To: Gowri Shankar ; QEMU Developers
; qemu-arm
Cc: qemu-disc...@nongnu.org; Konrad, Frederic ;
Iglesias, Francisco ; Alistair Francis
Subject: Re: REG: TTC Timer
On 22/11/22 12:27, Gowri Shankar
"%s: invalid command: %u",
> __func__, cmd);
> +return;
> }
>
> s->core_registers[DP_INTERRUPT_SIGNAL_STATE] |= 0x04;
> --
> 2.25.1
>
Looks good to me.
Reviewed-by: Frederic Konrad
> -Original Message-
> From: Peter Maydell
> Sent: 02 August 2022 15:34
> To: Konrad, Frederic
> Cc: qemu-devel@nongnu.org; Fabien Chouteau ;
> Frederic Konrad ; f4...@amsat.org
> Subject: Re: [PATCH for-7.1] hw/misc/grlib_ahb_apb_pnp: Support 8 and 16
> bit acc
Hi Peter,
CC'ing Philippe.
> -Original Message-
> From: Qemu-devel bounces+fkonrad=amd@nongnu.org> On Behalf Of Peter Maydell
> Sent: 02 August 2022 14:19
> To: qemu-devel@nongnu.org
> Cc: Fabien Chouteau ; Frederic Konrad
>
> Subject: [PATCH for-7
Hi Gregg,
AFAIK the leon3-generic can emulate the GR712RC with some little differences in
the memorymap and / or timer / CPU count. (You should be able to boot the
Gaisler monocore linux with it).
About the SMP support AdaCore had a few patches for it, I'll let Fabien answer.
Regards,Fred
> -Original Message-
> From: Peter Maydell
> Sent: 06 June 2022 11:20
> To: Frederic Konrad
> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org;
> edgar.igles...@gmail.com; alist...@alistair23.me; Sai Pavan Boddu
> ; Edgar Iglesias ;
> fkon...@amd.com
> Subje
> -Original Message-
> From: Peter Maydell
> Sent: 23 May 2022 14:52
> To: Frederic Konrad
> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org;
> edgar.igles...@gmail.com; alist...@alistair23.me; Sai Pavan Boddu
> ; Edgar Iglesias ; Sai Pavan Boddu
> ; Edgar
oduce xlnx-dp")
Signed-off-by: Frederic Konrad
Reviewed-by: Edgar E. Iglesias
---
hw/display/xlnx_dp.c | 17 ++---
include/hw/display/xlnx_dp.h | 9 +++--
2 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c
i
From: Sai Pavan Boddu
Add a periodic timer which raises vblank at a frequency of 30Hz.
Signed-off-by: Sai Pavan Boddu
Signed-off-by: Edgar E. Iglesias
Changes by fkonrad:
- Switched to transaction-based ptimer API.
- Added the DP_INT_VBLNK_START macro.
Signed-off-by: Frederic Konrad
last patches.
Tested by booting Petalinux with the framebuffer enabled.
Best Regards,
Fred
v1 -> v2:
* Better use of the ptimer API by using a correct POLICY as suggested
by Peter Maydell (Patch 2).
* Rebased on 78ac2eeb.
Frederic Konrad (2):
xlnx_dp: fix the wrong register s
From: Sai Pavan Boddu
Fix interrupt disable logic. Mask value 1 indicates that interrupts are
disabled.
Signed-off-by: Sai Pavan Boddu
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Frederic Konrad
---
hw/display/xlnx_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
igned-off-by: Frederic Konrad
Reviewed-by: Edgar E. Iglesias
---
hw/arm/xlnx-zynqmp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 375309e68e..383e177a00 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -
> -Original Message-
> From: Peter Maydell
> Sent: 16 May 2022 10:57
> To: Frederic Konrad
> Cc: qemu-devel@nongnu.org; alist...@alistair23.me;
> edgar.igles...@gmail.com; qemu-...@nongnu.org; Sai Pavan Boddu
> ; Edgar Iglesias ;
> fkon...@amd.com; Sai Pava
.@alistair23.me; edgar.igles...@gmail.com;
> peter.mayd...@linaro.org; qemu-...@nongnu.org; Sai Pavan Boddu
> ; Edgar Iglesias ;
> fkon...@amd.com
> Subject: [PATCH v1 0/4] xlnx-zcu102: fix the display port.
>
> From: Frederic Konrad
>
> Hi,
>
> This patch set fixes so
@gmail.com; Francisco Eduardo Iglesias
> ; Sai Pavan Boddu ; Frederic
> Konrad ; Edgar Iglesias ;
> edgar.igles...@amd.com
> Subject: [PATCH v1 4/4] hw/arm: versal: Connect the CRL
>
> From: "Edgar E. Iglesias"
>
> Connect the CRL (Clock Reset LPD) to the Versal
@gmail.com; Francisco Eduardo Iglesias
> ; Sai Pavan Boddu ; Frederic
> Konrad ; Edgar Iglesias ;
> edgar.igles...@amd.com
> Subject: [PATCH v1 3/4] hw/misc: Add a model of the Xilinx Versal CRL
>
> From: "Edgar E. Iglesias"
>
> Add a model of the Xilinx Versal
Iglesias
; Sai Pavan Boddu ; Frederic Konrad
; Edgar Iglesias ; edgar.igles...@amd.com
Subject: [PATCH v1 2/4] hw/arm: versal: Add the Cortex-R5Fs
From: "Edgar E. Iglesias"
Add the Cortex-R5Fs of the Versal RPU (Real-time Processing Unit) subsystem.
Signed-off-by: Edgar E. Iglesias
-
Iglesias
; Sai Pavan Boddu ; Frederic Konrad
; Edgar Iglesias ; edgar.igles...@amd.com
Subject: [PATCH v1 1/4] hw/arm: versal: Create an APU CPU Cluster
From: "Edgar E. Iglesias"
Create an APU CPU Cluster. This is in preparation to add the RPU.
Signed-off-by: Edgar E. Iglesias
---
h
Le 4/7/22 à 12:32, Peter Maydell a écrit :
On Tue, 14 Jun 2016 at 15:40, Peter Maydell wrote:
From: KONRAD Frederic
This is the implementation of the DisplayPort.
It has an aux-bus to access dpcd and edid.
Graphic plane is connected to the channel 3.
Video plane is connected to the
frederic.kon...@adacore.com and kon...@adacore.com will stop working starting
2022-04-01.
Use my personal email instead.
Signed-off-by: Frederic Konrad
---
.mailmap| 3 ++-
MAINTAINERS | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/.mailmap b/.mailmap
index
> -Original Message-
> From: Alex Bennée
> Konrad Schwarz writes:
>
> > static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
> > {
> > RISCVCPU *cpu = RISCV_CPU(cs);
> > @@ -163,21 +167,33 @@ static int riscv_gen_dynamic_csr
Hi,
> -Original Message-
> From: Richard Henderson
> Sent: Wednesday, January 5, 2022 0:02
> To: Schwarz, Konrad (T CED SES-DE) ;
> qemu-devel@nongnu.org
> Cc: Alistair Francis ; Bin Meng
> ; Palmer Dabbelt
> ; Ralf Ramsauer
> Subject: Re: [PATCH v2
Hi,
> -Original Message-
> From: Alistair Francis
> Sent: Tuesday, January 4, 2022 23:12
> To: Schwarz, Konrad (T CED SES-DE)
> Subject: Re: [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver
>
> On Wed, Jan 5, 2022 at 1:56 AM Konrad Schwarz
> wrote:
> > dif
> -Original Message-
> From: Alistair Francis
> Sent: Tuesday, January 4, 2022 23:03
> On Wed, Jan 5, 2022 at 1:55 AM Konrad Schwarz
> wrote:
> >
> > This is analog to the existing 'info mem' command and is implemented
> > using the
> -Original Message-
> From: Richard Henderson
> Sent: Tuesday, January 4, 2022 21:57
> Subject: Re: [PATCH v2 1/5] RISC-V: larger and more consistent register set
> for 'info registers'
>
> On 1/4/22 7:51 AM, Konrad Schwarz wrote:
> >
; advanced users can enable/disable register
groups as required.
Signed-off-by: Konrad Schwarz
---
target/riscv/cpu.c | 327 +
1 file changed, 303 insertions(+), 24 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f812998123..eb9
uest's 2nd level paging tables similarly to the
existing `info mem' command.
4) Improve QEMU RISC-V target descriptions for GDB. In particular, add
type information for many control and status registers.
5) Extend the virtual `priv' register with hypervisor virtualization status.
esents virtual debug registers in the `org.gnu.gdb.riscv.virtual'
feature of RISC-V target descriptions.
This patch adds the `v' (hypervisor virtualization mode) bit
to `priv' as specified by section 4.9.1 of version 1.0 of the
RISC-V Debug Support specification.
Signed-off-by: Konra
set of the RISC-V Control and Status Registers (CSRs).
Signed-off-by: Konrad Schwarz
---
target/riscv/csr.c| 2 +
target/riscv/csr32-op-gdbserver.h | 109 ++
target/riscv/csr64-op-gdbserver.h | 76 +++
target/riscv/gdb_csr_type_group.c | 16 ++
ta
This is analog to the existing 'info mem' command and is implemented
using the same machinery.
Signed-off-by: Konrad Schwarz
---
hmp-commands-info.hx | 16 +
include/monitor/hmp-target.h | 2 +
target/riscv/monitor.c | 135 +-
Enable the print (p) command to display both
general-purpose and Contral and Status (CSR) registers.
General purpose registers can be named using the xN form
or their ABI names (zero, ra, sp, a0, s1, t2).
Signed-off-by: Konrad Schwarz
---
target/riscv/monitor.c | 69
ing `info mem' command.
4) Improve QEMU RISC-V target descriptions for GDB. In particular, add
type information for many control and status registers.
5) Extend the virtual `priv' register with hypervisor virtualization status.
Konrad Schwarz (5):
RISC-V: larger and more consiste
set of the RISC-V Control and Status Registers (CSRs).
Signed-off-by: Konrad Schwarz
---
target/riscv/csr.c| 2 +
target/riscv/csr32-op-gdbserver.h | 109 ++
target/riscv/csr64-op-gdbserver.h | 76 +++
target/riscv/gdb_csr_types.c
This is analog to the existing 'info mem' command and is implemented
using the same machinery.
Signed-off-by: Konrad Schwarz
---
hmp-commands-info.hx | 16 +
include/monitor/hmp-target.h | 2 +
target/riscv/monitor.c | 135 +-
Enable the print (p) command to display both
general-purpose and Contral and Status (CSR) registers.
General purpose registers can be named using the xN form
or their ABI names (zero, ra, sp, a0, s1, t2).
Signed-off-by: Konrad Schwarz
---
target/riscv/monitor.c | 69
esents virtual debug registers in the `org.gnu.gdb.riscv.virtual'
feature of RISC-V target descriptions.
This patch adds the `v' (hypervisor virtualization mode) bit
to `priv' as specified by section 4.9.1 of version 1.0 of the
RISC-V Debug Support specification.
Signed-off-by: Konra
; advanced users can enable/disable register
groups as required.
Signed-off-by: Konrad Schwarz
---
target/riscv/cpu.c | 327 +
1 file changed, 303 insertions(+), 24 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f812998123..eb9
peripheral is not implemented, simply
log the opcode as unimplemented and keep going.
Reported-by: Fred Konrad
Signed-off-by: Philippe Mathieu-Daudé
---
target/avr/helper.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/avr/helper.c b/target/avr/helper.c
index 35e101
Le 4/30/21 à 12:27 PM, Joaquin de Andres a écrit :
On 4/28/21 9:17 PM, Philippe Mathieu-Daudé wrote:
Cc'ing Joaquín.
On 4/28/21 9:15 PM, Frederic Konrad wrote:
According to the as documentation:
(https://sourceware.org/binutils/docs-2.36/as/AVR-Options.html)
"Instruction se
Le 5/2/21 à 10:10 PM, Michael Rolnik a écrit :
Signed-off-by: Michael Rolnik
---
hw/avr/Kconfig| 1 +
hw/avr/atmega.c | 15 ++-
hw/avr/atmega.h | 2 +
hw/watchdog/Kconfig | 3 +
hw/watchdog/avr_wdt.c | 190
Hi Michael,
Le 5/2/21 à 10:10 PM, Michael Rolnik a écrit :
1. Initial implementation of AVR WDT
Nice!
There are two issues with this implementation so I need your help here
a. when I configure the WDT to fire an interrupt every 15ms it actually
happens every 6 instructions
Test
o test.elf
$ qemu-system-avr -serial mon:stdio -nographic -no-reboot -M mega \
-bios test.elf
qemu-system-avr: Current machine: Arduino Mega (ATmega1280) with 'avr6' CPU
qemu-system-avr: ELF image 'test.elf' is for 'avr51' CPU
So this fixes the atmega1280
Le 4/28/21 à 8:17 PM, Michael Rolnik a écrit :
Hi Fred.
How can I reproduce it?
Thank you.
Michael Rolnik
Hi Michael,
First sorry for the patchew noise, I didn't meant to sent a patch just an
inlined diff.
For the reproducer, that's pretty straight-forward with v6.0.0-rc5:
$ cat > foo.S
Le 4/28/21 à 4:16 PM, Philippe Mathieu-Daudé a écrit :
We are going to move this code, fix its style first.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: KONRAD Frederic
---
hw/sparc64/sparc64.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw
Le 4/28/21 à 4:16 PM, Philippe Mathieu-Daudé a écrit :
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: KONRAD Frederic
---
hw/sparc64/sparc64.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
index e3f9219a101..cc0b9bd30d3 100644
Hi,
I fall on a segfault while running the wdr instruction on AVR:
(gdb) bt
#0 0xadd0b23a in gdb_get_cpu_pid (cpu=0xaf5a4af0) at
../gdbstub.c:718
#1 0xadd0b2dd in gdb_get_cpu_process (cpu=0xaf5a4af0) at
../gdbstub.c:743
#2 0xadd0e47
7;t rename them).
leon3_irq_ack() is now locally used, declare it static to reduce
its scope.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: KONRAD Frederic
Tested-by: KONRAD Frederic
Thanks for the fix!
---
RFC: The problem is we have hardware specific code in the
architectural translati
Le 4/27/21 à 9:26 PM, Philippe Mathieu-Daudé a écrit :
This series fixes link failure when building either the leon3
machine or the sun4m ones.
The problem is we have hardware specific code in the architectural
translation code. Move this code to hw/sparc/.
The link failures can be reproduce
Le 12/12/20 à 3:41 PM, Peter Maydell a écrit :
Currently the GRLIB_IRQMP device is used in one place (the leon3
board), but instead of the device providing inbound gpio lines for
the board to wire up, the board code itself calls
qemu_allocate_irqs() with the handler function being a set_irq
fu
int intno);
/* GPTimer */
Reviewed-by: KONRAD Frederic
GRLIB_VENDOR_GAISLER, GRLIB_APBUART_DEV, 1,
LEON3_UART_IRQ, GRLIB_APBIO_AREA);
LGTM, thanks!
Reviewed-by: KONRAD Frederic
s.
>
> Signed-off-by: Prasad J Pandit
Reviewed-by: Konrad Rzeszutek Wilk
Thank you!
s.
>
> Signed-off-by: Prasad J Pandit
Thank you for doing it!
Reviewed-by: Konrad Rzeszutek Wilk
with one change below.
> ---
> contribute/security-process.md | 134 -
> 1 file changed, 80 insertions(+), 54 deletions(-)
>
> Update v1: incorp
. monster snip..
> > Maybe we could start with a moderated list and improvise as we go forward?
>
> I really think that encryption of the details of a vulnerability is
> important, if somehow it gets intercepted - which is not that difficult
> with e-mail - then there is the potential for a malici
Le 6/26/20 à 12:06 PM, Fred Konrad a écrit :
Le 6/16/20 à 4:52 PM, Alex Bennée a écrit :
kon...@adacore.com writes:
From: KONRAD Frederic
With that we can just use chardev=serial0.
I don't quite follow what this means.
./aarch64-softmmu/qemu-system-aarch64 -cpu max -monitor
Hi Corey,
Le 6/22/20 à 11:32 PM, Corey Minyard a écrit :
On Sun, Jun 21, 2020 at 04:43:38PM +0200, BALATON Zoltan wrote:
These functions have a parameter that decides the direction of
transfer but totally confusingly they don't match but inverted sense.
To avoid frequent mistakes when using t
Le 6/16/20 à 4:52 PM, Alex Bennée a écrit :
kon...@adacore.com writes:
From: KONRAD Frederic
With that we can just use chardev=serial0.
I don't quite follow what this means.
./aarch64-softmmu/qemu-system-aarch64 -cpu max -monitor none -chardev=serial0
-M virt -display
Missed this one sorry.
Le 6/12/20 à 10:31 AM, Laurent Vivier a écrit :
Le 28/04/2020 à 19:17, KONRAD Frederic a écrit :
The MC68881 say about infinities (3.2.4):
"*For the extended precision format, the most significant bit of the
mantissa (the integer bit) is a don't car
From: KONRAD Frederic
With that we can just use chardev=serial0.
Signed-off-by: KONRAD Frederic
---
softmmu/vl.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/softmmu/vl.c b/softmmu/vl.c
index f669c06..9b8b48a 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -4123,8
From: KONRAD Frederic
Don't send the trailing 0 from the string.
Signed-off-by: KONRAD Frederic
---
hw/semihosting/console.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/semihosting/console.c b/hw/semihosting/console.c
index 22e7827..9b4fee9 100644
---
3_UART_OFFSET, 0xFFF,
+GRLIB_VENDOR_GAISLER, GRLIB_APBUART_DEV, 1,
+LEON3_UART_IRQ, GRLIB_APBIO_AREA);
}
static void leon3_generic_machine_init(MachineClass *mc)
Reviewed-by: KONRAD Frederic
Thanks!
Le 5/18/20 à 3:50 PM, Philippe Mathieu-Daudé a écrit :
On 5/18/20 3:02 PM, kon...@adacore.com wrote:
From: KONRAD Frederic
This have been introduced by:
8de702cb677c8381fb702cae252d6b69aa4c653b
It doesn't seem to be used so remove it.
Signed-off-by: KONRAD Frederic
---
Le 5/28/20 à 2:00 PM, Philippe Mathieu-Daudé a écrit :
Hi Fred,
On 5/28/20 11:44 AM, Fred Konrad wrote:
Hi all,
Just wonderring if there is any reason not to be able to defer
qemu_semihosting_connect_chardevs a little more to be able to specify
chardev=serial0?
Like:
diff --git a/softmmu
Hi all,
Just wonderring if there is any reason not to be able to defer
qemu_semihosting_connect_chardevs a little more to be able to specify
chardev=serial0?
Like:
diff --git a/softmmu/vl.c b/softmmu/vl.c
index 6390cf0..9fa1553 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -4333,8 +4333,6 @@
/20 9:03 AM, Philippe Mathieu-Daudé wrote:
On 4/14/20 12:00 PM, KONRAD Frederic wrote:
Le 4/13/20 à 11:07 PM, Philippe Mathieu-Daudé a écrit :
[Cc'ing Peter]
On 4/13/20 12:12 PM, KONRAD Frederic wrote:
Le 4/11/20 à 7:30 PM, Philippe Mathieu-Daudé a écrit :
On 3/31/20 12:50 PM, Philippe Mat
From: KONRAD Frederic
This have been introduced by:
8de702cb677c8381fb702cae252d6b69aa4c653b
It doesn't seem to be used so remove it.
Signed-off-by: KONRAD Frederic
---
hw/semihosting/console.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/semihosting/console.c b/hw/semiho
I wasn't aware of this mailmap stuff.
Le 5/18/20 à 12:39 PM, Philippe Mathieu-Daudé a écrit :
Update Fred Konrad email address to avoid emails bouncing.
Signed-off-by: Philippe Mathieu-Daudé
---
.mailmap | 1 +
1 file changed, 1 insertion(+)
diff --git a/.mailmap b/.mailmap
en missing these
two devices, yet nobody noticed.
I can't tell, but it used to work back in 2016 since these devices were required
to have a working framebuffer.
Fix by realizing them in xlnx_dp_realize().
Fixes: 58ac482a66de09a7590f705e53fc6a3fb8a055e8
Cc: KONRAD Frederic
Cc: Alist
c. Visible in "info qtree":
bus: main-system-bus
type System
+ dev: grlib,ahbpnp, id ""
+mmio f000/1000
+ dev: grlib,apbpnp, id ""
+mmio 800ff000/1000
dev: grlib,irqmp, id &quo
Le 4/29/20 à 10:42 AM, Laurent Vivier a écrit :
Le 28/04/2020 à 19:17, KONRAD Frederic a écrit :
The MC68881 say about infinities (3.2.4):
"*For the extended precision format, the most significant bit of the
mantissa (the integer bit) is a don't care."
https://www.nxp.com/do
Le 4/29/20 à 11:38 AM, Laurent Vivier a écrit :
Le 29/04/2020 à 11:28, Alex Bennée a écrit :
Laurent Vivier writes:
Le 28/04/2020 à 19:17, KONRAD Frederic a écrit :
Currently "cf-core.xml" is sent to GDB when using any m68k flavor. Thing is
it uses the "org.gnu.gd
fmoved %fp@(-8), %fp0
1: $fp0 = inf
(gdb) si
end () at main.S:12
12 bra end
1: $fp0 = nan(0xf800)
(gdb) x/1xg $fp-8
0x4120 : 0x7fff
Signed-off-by: KONRAD Frederic
---
include/fpu/softfloat.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/
DEFINE_M68K_CPU_TYPE_CF and dropped
DEFINE_M68K_CPU_TYPE_WITH_CLASS (Suggested by Laurent)
* target/m68k/cpu.c: reworked DEFINE_M68K_CPU_TYPE_* to guess the
cpu_initfn from the cpu_model (Suggested by Laurent).
Cheers,
Fred
KONRAD Frederic (2):
softfloat
ng the "file" command.
0x in ?? ()
(gdb) p $fp0
$1 = nan(0x)
Signed-off-by: KONRAD Frederic
---
configure | 2 +-
gdb-xml/m68k-core.xml | 29
target/m68k/cpu.c | 52 ---
Le 4/28/20 à 4:13 PM, Laurent Vivier a écrit :
Le 28/04/2020 à 15:19, KONRAD Frederic a écrit :
Le 4/27/20 à 9:53 AM, Laurent Vivier a écrit :
Le 20/04/2020 à 16:01, frederic.kon...@adacore.com a écrit :
From: KONRAD Frederic
...
I would prefer to have two macros with no class
Le 4/27/20 à 9:53 AM, Laurent Vivier a écrit :
Le 20/04/2020 à 16:01, frederic.kon...@adacore.com a écrit :
From: KONRAD Frederic
Currently "cf-core.xml" is sent to GDB when using any m68k flavor. Thing is
it uses the "org.gnu.gdb.coldfire.core" feature name and gd
Le 4/20/20 à 10:43 PM, Laurent Vivier a écrit :
Le 20/04/2020 à 21:08, KONRAD Frederic a écrit :
Le 4/20/20 à 5:46 PM, Laurent Vivier a écrit :
Le 20/04/2020 à 16:01, frederic.kon...@adacore.com a écrit :
From: KONRAD Frederic
Currently "cf-core.xml" is sent to GDB when usin
Le 4/20/20 à 5:46 PM, Laurent Vivier a écrit :
Le 20/04/2020 à 16:01, frederic.kon...@adacore.com a écrit :
From: KONRAD Frederic
Currently "cf-core.xml" is sent to GDB when using any m68k flavor. Thing is
it uses the "org.gnu.gdb.coldfire.core" feature name and gd
Le 4/20/20 à 6:13 PM, Alex Bennée a écrit :
frederic.kon...@adacore.com writes:
From: KONRAD Frederic
Currently "cf-core.xml" is sent to GDB when using any m68k flavor. Thing is
it uses the "org.gnu.gdb.coldfire.core" feature name and gdb 8.3 then expects
a coldfir
From: KONRAD Frederic
Currently "cf-core.xml" is sent to GDB when using any m68k flavor. Thing is
it uses the "org.gnu.gdb.coldfire.core" feature name and gdb 8.3 then expects
a coldfire FPU instead of the default m68881 FPU.
This is not OK because the m68881 floats regist
Le 4/16/20 à 1:18 PM, Laurent Vivier a écrit :
Le 14/04/2020 à 18:56, Alex Bennée a écrit :
Philippe Mathieu-Daudé writes:
gdbstub/m68k seems broken with floats, previous to refactor commit
a010bdbe719 ("extend GByteArray to read register helpers").
HEAD at 6fb1603aa2:
$ qemu-system-m68
Le 4/13/20 à 11:07 PM, Philippe Mathieu-Daudé a écrit :
[Cc'ing Peter]
On 4/13/20 12:12 PM, KONRAD Frederic wrote:
Le 4/11/20 à 7:30 PM, Philippe Mathieu-Daudé a écrit :
On 3/31/20 12:50 PM, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (7):
hw/misc/grlib_ahb_apb_pnp:
Le 4/11/20 à 7:30 PM, Philippe Mathieu-Daudé a écrit :
On 3/31/20 12:50 PM, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (7):
hw/misc/grlib_ahb_apb_pnp: Avoid crash when writing to AHB PnP
registers
hw/misc/grlib_ahb_apb_pnp: Fix AHB PnP 8-bit accesses
Ping ^^^ for 5.0?
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