errors, it builds on 32 & 64 bit
on my system. Cheers
As for the Signed-off-by, I'd rather not, and the contributing guide does not
require it.
Regards,
Julia
future, incorrectly set up page
tables can be debugged without bisecting QEMU.
Signed-off-by: julia
---
target/riscv/cpu_helper.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e1dfc4ecbf
future, incorrectly set up page
tables can be debugged without bisecting QEMU.
Signed-off-by: julia
---
target/riscv/cpu_helper.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e1dfc4ecbf
fY3jfRbpdO9l1l2wwDZ2l0AAZzaGE1MTIAAABTC3NzaC1lZDI1NTE5
QP6c2B82m4kq6h046Ou/LV6c9I/D/uUtUlivmbvR/lSdCWOiPIYnpK5HPtvhcgVYoQ
8X1k8kKjplch4iy6JnNgU=
-END SSH SIGNATURE-
julia (1):
target/riscv: log guest errors when reserved bits are set in PTEs
target/riscv
.
This series is to support handling the new virtgpu command from the guest
VM to get the physical p2pdma_distance of two PCI devices of guest VM.
Julia Zhang (3):
virtio-gpu: set hostaddr for virtio iGPU
pci: introduce a function to get PCIDevice
virtio-gpu: add a new command to calculate
To implement passthrough dGPU prime in guest, virtio-gpu need to check
p2pdma_distance of two GPUs. This adds a new command for guest to pass
virtual pci notations of two pci devices to host and send xen privcmd to
calculate physical p2pdma_distance.
Signed-off-by: Julia Zhang
---
hw/display
Introduce a helper function to get PCIDevice from qdev pci notation.
Signed-off-by: Julia Zhang
---
hw/pci/pci.c | 22 ++
include/hw/pci/pci.h | 2 ++
2 files changed, 24 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 1416ae202c..95806ead4f 100644
Get physical pci notation from hvm file and set hostaddr for virtio
iGPU.
Signed-off-by: Julia Zhang
---
hw/display/virtio-gpu.c| 6 ++
hw/xen/xen_pt.c| 10 +-
hw/xen/xen_pt.h| 1 -
include/hw/pci/pci_device.h| 1 +
include/hw/virtio
, or just leave it to the
standard PCI IRQ traces.
Julia
On Tue, 15 Oct 2024, at 21:33, julia wrote:
> The NVMe subsystem logs "pulsing IRQ pin" when it is asserting the PCI(e)
> IRQ. This is confusing as it implies a short pulse, not the level-triggered
> interrupt
The NVMe subsystem logs "pulsing IRQ pin" when it is asserting the PCI(e)
IRQ. This is confusing as it implies a short pulse, not the level-triggered
interrupts PCI(e) uses.
Also remove the pci_irq_pulse() function marked with FIXME as it is no
longer used by any calls.
Signed-off
This is necessary to provide discernible error messages to the caller.
Signed-off-by: Julia Suvorova
Reviewed-by: Peter Xu
---
accel/kvm/kvm-all.c| 41 +-
include/sysemu/kvm.h | 4 ++--
target/arm/kvm.c | 4 ++--
target/i386/kvm
.
[1] https://issues.redhat.com/browse/RHEL-7558
[2] 7191f24c7fcf "accel/kvm/kvm-all: Handle register access errors"
--
v2:
* made all reports as error_reportf_err() and fixed prefixes [Peter]
Julia Suvorova (2):
kvm: Allow kvm_arch_get/put_registers to accept Error**
targe
: Julia Suvorova
Reviewed-by: Peter Xu
---
target/i386/kvm/kvm.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index 039ed08825..7cdc87f855 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -5133,6 +5133,7
On Wed, Sep 25, 2024 at 8:53 PM Peter Xu wrote:
>
> On Wed, Sep 25, 2024 at 05:36:22PM +0200, Julia Suvorova wrote:
> > This is necessary to provide discernible error messages to the caller.
> >
> > Signed-off-by: Julia Suvorova
>
> Reviewed-by: P
: Julia Suvorova
---
target/i386/kvm/kvm.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index 039ed08825..7cdc87f855 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -5133,6 +5133,7 @@ int
.
[1] https://issues.redhat.com/browse/RHEL-7558
[2] 7191f24c7fcf "accel/kvm/kvm-all: Handle register access errors"
Julia Suvorova (2):
kvm: Allow kvm_arch_get/put_registers to accept Error**
target/i386/kvm: Report which action failed in
kvm_arch_put/get_registers
accel/kvm
This is necessary to provide discernible error messages to the caller.
Signed-off-by: Julia Suvorova
---
accel/kvm/kvm-all.c| 41 +-
include/sysemu/kvm.h | 4 ++--
target/arm/kvm.c | 4 ++--
target/i386/kvm/kvm.c | 4
Hi all,
Sorry to late reply. This is v2 of the implementation of
resource_query_layout. This adds a new ioctl to let guest query information
of host resource, which is originally from Daniel Stone. We add some
changes to support query the correct stride of host resource before it's
created, which
From: Daniel Stone
A new ioctl to shuttle information between host and guest about the
actual buffer allocation, which can be used for interop between GL and
Vulkan when supporting standard window systems.
Signed-off-by: Daniel Stone
Co-developed-by: Julia Zhang
Signed-off-by: Julia Zhang
From: Daniel Stone
A new ioctl to shuttle information between host and guest about the
actual buffer allocation, which can be used for interop between GL and
Vulkan when supporting standard window systems.
---
hw/display/virtio-gpu-base.c| 4 ++
hw/display/virtio-gpu-virgl.c
Modify resource_query_layout to handle the use case that need to query
correct stride for guest linear resource before it is created.
Signed-off-by: Julia Zhang
---
hw/display/virtio-gpu-virgl.c | 20 +++-
include/standard-headers/linux/virtio_gpu.h | 8
/-/merge_requests/23896
virglrenderer mr: https:
//gitlab.freedesktop.org/virgl/virglrenderer/-/merge_requests/1268
Daniel Stone (1):
virgl: Implement resource_query_layout
Julia Zhang (1):
virgl: Modify resource_query_layout
hw/display/virtio-gpu-base.c| 4 +++
hw/display/virtio-gpu
On Thu, Jun 22, 2023 at 7:48 PM Michael S. Tsirkin wrote:
>
> On Thu, Jun 22, 2023 at 05:46:40PM +0200, Julia Suvorova wrote:
> > On Thu, Jun 22, 2023 at 12:34 PM Ani Sinha wrote:
> > >
> > > PCI Express ports only have one slot, so PCI Express devices can only be
gt;
> > > I make use of the find_q35() function in later patches, but I agree now a
> > majority of this patch is a bit different.
>
> There is likely an existing alternative already. (probably introduced by ACPI
> PIC hotplug for q35)
There is a similar function acpi_get_
; +error_setg(errp, "PCI: slot %d is not valid for %s,"
> + " PCI express devices can only be plugged into slot 0.",
This is not technically correct, because downstream ports and root
ports are also PCIe devices, and they can have di
: add core_count2 to smbios table type 4")
Resolves: https://bugzilla.redhat.com/show_bug.cgi?id=2169904
Signed-off-by: Julia Suvorova
---
v2:
* add fixes tag
* check tbl_len instead of ep_type
hw/smbios/smbios.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a
/show_bug.cgi?id=2169904
Signed-off-by: Julia Suvorova
---
hw/smbios/smbios.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
index b4243de735..903fd22350 100644
--- a/hw/smbios/smbios.c
+++ b/hw/smbios/smbios.c
@@ -749,14 +749,16
ng Structure "NVDIMM State Flags" Bit 3
Fixes: dbd730e859 ("nvdimm: check -object memory-backend-file, readonly=on
option")
Signed-off-by: Julia Suvorova
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Pankaj Gupta
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: David Hildenbrand
--
On Tue, Oct 18, 2022 at 6:49 PM Michael S. Tsirkin wrote:
>
> On Tue, Oct 18, 2022 at 06:17:55PM +0200, Philippe Mathieu-Daudé wrote:
> > On 18/10/22 17:25, Julia Suvorova wrote:
> > > In the ACPI specification [1], the 'unarmed' bit is set when a device
> &g
ng Structure "NVDIMM State Flags" Bit 3
Signed-off-by: Julia Suvorova
Reviewed-by: Stefan Hajnoczi
---
hw/mem/nvdimm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/mem/nvdimm.c b/hw/mem/nvdimm.c
index 7c7d81..bfb76818c1 100644
--- a/hw/mem/nvdimm.c
+++ b/hw
on of the structure loop
[Ani]
Julia Suvorova (5):
hw/smbios: add core_count2 to smbios table type 4
bios-tables-test: teach test to use smbios 3.0 tables
tests/acpi: allow changes for core_count2 test
bios-tables-test: add test for number of cores > 255
tests/acpi: update tables for
The new test is run with a large number of cpus and checks if the
core_count field in smbios_cpu_test (structure type 4) is correct.
Choose q35 as it allows to run with -smp > 255.
Signed-off-by: Julia Suvorova
Message-Id: <20220731162141.178443-5-jus...@redhat.com>
---
tests/qtest/bi
Introduce the 64-bit entry point. Since we no longer have a total
number of structures, stop checking for the new ones at the EOF
structure (type 127).
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
Message-Id: <20220731162141.178443-3-jus...@redhat.com>
---
tests/qtest/bios-
_OST: OSPM Status Indication
+{
+COST (0xFF, Arg0, Arg1, Arg2)
+}
+}
+
...
Signed-off-by: Julia Suvorova
Message-Id: <20220731162141.178443-6-jus...@redhat.com>
---
tests/data/acpi/q35/APIC.core-count2| Bin 0 -> 2478 byt
Signed-off-by: Julia Suvorova
Message-Id: <20220731162141.178443-4-jus...@redhat.com>
---
tests/data/acpi/q35/APIC.core-count2| 0
tests/data/acpi/q35/DSDT.core-count2| 0
tests/data/acpi/q35/FACP.core-count2| 0
tests/qtest/bios-tables-test-allowed-diff.h | 3
.
core_enabled2 and thread_count2 fields work the same way.
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
Message-Id: <20220731162141.178443-2-jus...@redhat.com>
---
hw/smbios/smbios.c | 19 ---
hw/smbios/smbios_build.h | 9 +++--
include/hw/fi
Signed-off-by: Julia Suvorova
---
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
tests/data/acpi/q35/APIC.core-count2| 0
tests/data/acpi/q35/DSDT.core-count2| 0
tests/data/acpi/q35/FACP.core-count2| 0
4 files changed, 3 insertions(+)
create mode 100644 tests
Introduce the 64-bit entry point. Since we no longer have a total
number of structures, stop checking for the new ones at the EOF
structure (type 127).
Signed-off-by: Julia Suvorova
---
tests/qtest/bios-tables-test.c | 95 +-
1 file changed, 71 insertions(+), 24
The new test is run with a large number of cpus and checks if the
core_count field in smbios_cpu_test (structure type 4) is correct.
Choose q35 as it allows to run with -smp > 255.
Signed-off-by: Julia Suvorova
---
tests/qtest/bios-tables-test.c | 53 +-
1 f
_OST: OSPM Status Indication
+{
+COST (0xFF, Arg0, Arg1, Arg2)
+}
+}
+
...
Signed-off-by: Julia Suvorova
---
tests/qtest/bios-tables-test-allowed-diff.h | 3 ---
tests/data/acpi/q35/APIC.core-count2| Bin 0 -> 2478 bytes
te
ad of creating new constants
* refactor smbios_cpu_test [Igor, Ani]
* clarify signature check [Igor]
* add comments with specifications and clarification of the structure loop
[Ani]
Julia Suvorova (5):
hw/smbios: add core_count2 to smbios table type 4
bios-tables-test: teach test t
.
core_enabled2 and thread_count2 fields work the same way.
Signed-off-by: Julia Suvorova
---
hw/smbios/smbios_build.h | 9 +++--
include/hw/firmware/smbios.h | 11 +++
hw/smbios/smbios.c | 18 +++---
3 files changed, 33 insertions(+), 5 deletions(-)
diff
On Tue, Jun 14, 2022 at 11:50 AM David Hildenbrand wrote:
>
> On 14.06.22 10:54, Igor Mammedov wrote:
> > On Mon, 13 Jun 2022 16:09:53 +0100
> > Stefan Hajnoczi wrote:
> >
> >> On Mon, Jun 13, 2022 at 05:01:10PM +0200, Julia Suvorova wrote:
> >>> On
On Tue, May 31, 2022 at 5:32 PM Stefan Hajnoczi wrote:
>
> On Tue, May 31, 2022 at 04:51:47PM +0200, Julia Suvorova wrote:
> > In the ACPI specification [1], the 'unarmed' bit is set when a device
> > cannot accept a persistent write. This means that when a memdev is
On Thu, Jun 2, 2022 at 5:20 PM Igor Mammedov wrote:
>
> On Fri, 27 May 2022 18:56:50 +0200
> Julia Suvorova wrote:
>
> > The new test is run with a large number of cpus and checks if the
> > core_count field in smbios_cpu_test (structure type 4) is correct.
> >
>
On Thu, Jun 2, 2022 at 4:35 PM Igor Mammedov wrote:
>
> On Thu, 2 Jun 2022 16:31:25 +0200
> Igor Mammedov wrote:
>
> > On Tue, 31 May 2022 14:40:15 +0200
> > Julia Suvorova wrote:
> >
> > > On Sat, May 28, 2022 at 6:34 AM Ani Sinha wrote:
> > &g
On Thu, Jun 2, 2022 at 5:04 PM Igor Mammedov wrote:
>
> On Fri, 27 May 2022 18:56:48 +0200
> Julia Suvorova wrote:
>
> > Introduce the 64-bit entry point. Since we no longer have a total
> > number of structures, stop checking for the new ones at the EOF
> > struct
On Tue, May 31, 2022 at 3:14 PM Ani Sinha wrote:
>
> On Tue, May 31, 2022 at 5:53 PM Julia Suvorova wrote:
> >
> > On Sat, May 28, 2022 at 7:22 AM Ani Sinha wrote:
> > >
> > >
> > >
> > > On Fri, 27 May 2022, Julia Suvorova wrote:
> &g
ng Structure "NVDIMM State Flags" Bit 3
Signed-off-by: Julia Suvorova
---
hw/mem/nvdimm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/mem/nvdimm.c b/hw/mem/nvdimm.c
index 7c7d81..bfb76818c1 100644
--- a/hw/mem/nvdimm.c
+++ b/hw/mem/nvdimm.c
@
On Sat, May 28, 2022 at 6:34 AM Ani Sinha wrote:
>
>
>
> On Fri, 27 May 2022, Julia Suvorova wrote:
>
> > In order to use the increased number of cpus, we need to bring smbios
> > tables in line with the SMBIOS 3.0 specification. This allows us to
> > intr
On Sat, May 28, 2022 at 7:22 AM Ani Sinha wrote:
>
>
>
> On Fri, 27 May 2022, Julia Suvorova wrote:
>
> > The new test is run with a large number of cpus and checks if the
> > core_count field in smbios_cpu_test (structure type 4) is correct.
> >
> > Choose
On Mon, May 30, 2022 at 8:11 AM Ani Sinha wrote:
>
> On Fri, May 27, 2022 at 10:27 PM Julia Suvorova wrote:
> >
> > Introduce the 64-bit entry point. Since we no longer have a total
> > number of structures, stop checking for the new ones at the EOF
> > structure
The new test is run with a large number of cpus and checks if the
core_count field in smbios_cpu_test (structure type 4) is correct.
Choose q35 as it allows to run with -smp > 255.
Signed-off-by: Julia Suvorova
---
tests/qtest/bios-tables-test.c | 35 +-
1 f
Signed-off-by: Julia Suvorova
---
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
tests/data/acpi/q35/APIC.core-count2| 0
tests/data/acpi/q35/DSDT.core-count2| 0
tests/data/acpi/q35/FACP.core-count2| 0
4 files changed, 3 insertions(+)
create mode 100644 tests
Introduce the 64-bit entry point. Since we no longer have a total
number of structures, stop checking for the new ones at the EOF
structure (type 127).
Signed-off-by: Julia Suvorova
---
tests/qtest/bios-tables-test.c | 101 -
1 file changed, 75 insertions(+), 26
...
Core Count: 24
Core Enabled: 24
Thread Count: 1
...
Big update in the bios-tables-test as it couldn't work with SMBIOS 3.0.
Julia Suvorova (5):
hw/smbios: add core_count2 to smbios table type 4
bios-tables-test: teach test to use smbios 3.0 tables
.
core_enabled2 and thread_count2 fields work the same way.
Signed-off-by: Julia Suvorova
---
include/hw/firmware/smbios.h | 3 +++
hw/smbios/smbios.c | 11 +--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/include/hw/firmware/smbios.h b/include/hw/firmware
EJx: Eject Device, x=0-9
+{
+CEJ0 (0xFF)
+}
+
+Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+{
+ COST (0x0101, Arg0, Arg1, Arg2)
+}
+}
...
Signed-off
hing KVM's limit is unblock upstream
> > > testing so it would be easier to push limits for others.
> > > Downstream can clamp that value down to whatever it deems as supported.
> > >
> > > > Going beyond 710 CPUs value requires using the SMBIOS 3 entry
On Wed, Nov 10, 2021 at 2:58 PM Igor Mammedov wrote:
>
> On Wed, 10 Nov 2021 02:21:34 -0500
> "Michael S. Tsirkin" wrote:
>
> > On Wed, Nov 10, 2021 at 06:30:13AM +0100, Julia Suvorova wrote:
> > > There are two ways to enable ACPI PCI Hot-plug:
> > >
:
--global ICH9-LPC.acpi-pci-hotplug-with-bridge-support=off
Change the bit in _OSC method so that the OS selects ACPI PCI Hot-plug
instead of PCIe Native.
[1] https://gitlab.com/qemu-project/qemu/-/issues/641
[2] https://bugzilla.redhat.com/show_bug.cgi?id=2006409
Signed-off-by: Julia
Prepare for changing the _OSC method in q35 DSDT.
Signed-off-by: Julia Suvorova
---
tests/qtest/bios-tables-test-allowed-diff.h | 16
1 file changed, 16 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index
Rename the option to better represent its function - toggle Hot-Plug
Capable bit in the PCIe Slot Capability.
Signed-off-by: Julia Suvorova
---
include/hw/pci/pcie_port.h | 2 +-
hw/i386/pc_q35.c | 2 +-
hw/pci-bridge/gen_pcie_root_port.c | 6 +-
hw/pci/pcie.c
Local0 &= 0x1F
+Local0 &= 0x1E
Signed-off-by: Julia Suvorova
---
tests/qtest/bios-tables-test-allowed-diff.h | 16
tests/data/acpi/q35/DSDT| Bin 8289 -> 8289 bytes
tests/data/acpi/q35/DSDT.acpihmat | Bin
oot-ports in 6.1 too.
[1] https://gitlab.com/qemu-project/qemu/-/issues/641
[2] https://bugzilla.redhat.com/show_bug.cgi?id=2006409
Signed-off-by: Julia Suvorova
---
include/hw/acpi/ich9.h | 1 +
hw/acpi/ich9.c | 18 ++
hw/i386/pc.c | 2 ++
hw/i386/pc_q35.c
g IO'
[2] https://gitlab.com/qemu-project/qemu/-/issues/641
[3] https://bugzilla.redhat.com/show_bug.cgi?id=2006409
Julia Suvorova (5):
hw/pci/pcie_port: Rename 'native-hotplug' to 'native-hpc-bit'
hw/acpi/ich9: Add compatibility option for 'native-hpc-bit'
b
.com/qemu-project/qemu/-/issues/641
> > >
> > > This regression is significant, because it has broken the out of the
> > > box default configuration that OpenStack uses for booting all VMs.
> > > They add 16 pcie-root-ports by defalt to allow empty slots for de
hange has been tested using a Windows Server 2019 guest VM. Windows
> no longer complains after this change.
>
> Fixes: caf108bc58790 ("hw/i386/acpi-build: Add ACPI PCI hot-plug methods to
> Q35")
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/561
>
>
=1752465
* https://bugzilla.redhat.com/show_bug.cgi?id=1690256
To return to PCIe Native hot-plug:
-global ICH9-LPC.acpi-pci-hotplug-with-bridge-support=off
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
---
hw/acpi/ich9.c | 2 +-
hw/i386/pc.c | 1 +
2 files changed, 2
}
+
...
+Method (DVNT, 2, NotSerialized)
+{
+If ((Arg0 & One))
+{
+Notify (S00, Arg1)
+}
...
Signed-off-by: Julia Suvorova
---
tests/qtest/bios-tables-test-allowed-diff.h | 11 ---
tests/dat
Implement notifications and gpe to support q35 ACPI PCI hot-plug.
Use 0xcc4 - 0xcd7 range for 'acpi-pci-hotplug' io ports.
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
Reviewed-by: Marcel Apfelbaum
---
hw/i386/acpi-build.h| 4
include/hw/acpi/ich9.h | 2 ++
e 'hotplug=off' on the port means all hot-plug types are disabled.
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
Reviewed-by: Marcel Apfelbaum
Reviewed-by: David Gibson
---
include/hw/pci/pcie_port.h | 5 -
hw/acpi/pcihp.c| 8
hw/core/machine.c
All DSDT Q35 tables will be modified because ACPI hot-plug is enabled
by default.
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
Reviewed-by: Marcel Apfelbaum
---
tests/qtest/bios-tables-test-allowed-diff.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/tests/qtest
Add acpi_pcihp to ich9_pm as part of
'acpi-pci-hotplug-with-bridge-support' option. Set default to false.
Signed-off-by: Julia Suvorova
Signed-off-by: Marcel Apfelbaum
Reviewed-by: Igor Mammedov
---
hw/i386/acpi-build.h| 1 +
include/hw/acpi/ich9.h | 3 ++
hw/acpi/acpi-x86-s
idges
* use 'acpi-root-pci-hotplug'
* add migration states [Igor]
* minor style changes
v2:
* new ioport range for acpiphp [Gerd]
* drop find_pci_host() [Igor]
* explain magic numbers in _OSC [Igor]
* drop build_q35_pci_hotplug() wrapper [Igor]
Julia Suvorova (6)
On Thu, Jul 1, 2021 at 6:59 AM David Gibson wrote:
>
> On Thu, Jun 17, 2021 at 09:07:35PM +0200, Julia Suvorova wrote:
> > Add acpi_pcihp to ich9_pm as part of
> > 'acpi-pci-hotplug-with-bridge-support' option. Set default to false.
> >
> > Signed-off-b
PCIE_SLOT property renamed to "native-hotplug" to be more concise
and consistent with other properties.
Signed-off-by: Julia Suvorova
---
hw/i386/pc_q35.c | 4 ++--
hw/pci/pcie_port.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/i386/pc_q35.c b/hw/i38
}
+
...
+Method (DVNT, 2, NotSerialized)
+{
+If ((Arg0 & One))
+{
+Notify (S00, Arg1)
+}
...
Signed-off-by: Julia Suvorova
---
tests/qtest/bios-tables-test-allowed-diff.h | 11 ---
tests/dat
e 'hotplug=off' on the port means all hot-plug types are disabled.
Signed-off-by: Julia Suvorova
---
include/hw/pci/pcie_port.h | 5 -
hw/acpi/pcihp.c| 8
hw/core/machine.c | 1 -
hw/i386/pc_q35.c | 11 +++
hw/pci/pcie.c
Implement notifications and gpe to support q35 ACPI PCI hot-plug.
Use 0xcc4 - 0xcd7 range for 'acpi-pci-hotplug' io ports.
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
---
hw/i386/acpi-build.h| 4
include/hw/acpi/ich9.h | 2 ++
include/hw/acpi/pcihp.h | 3 ++
=1752465
* https://bugzilla.redhat.com/show_bug.cgi?id=1690256
To return to PCIe Native hot-plug:
-global ICH9-LPC.acpi-pci-hotplug-with-bridge-support=off
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
---
hw/acpi/ich9.c | 2 +-
hw/i386/pc.c | 1 +
2 files changed, 2
All DSDT Q35 tables will be modified because ACPI hot-plug is enabled
by default.
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed
Add acpi_pcihp to ich9_pm as part of
'acpi-pci-hotplug-with-bridge-support' option. Set default to false.
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
---
hw/i386/acpi-build.h | 1 +
include/hw/acpi/ich9.h | 3 ++
hw/acpi/ich9.c
ci_hotplug() wrapper [Igor]
Julia Suvorova (7):
hw/acpi/pcihp: Enhance acpi_pcihp_disable_root_bus() to support Q35
hw/i386/acpi-build: Add ACPI PCI hot-plug methods to Q35
hw/acpi/ich9: Enable ACPI PCI hot-plug
hw/pci/pcie: Do not set HPC flag if acpihp is used
bios-tables-test: Allow
PCI Express does not allow hot-plug on pcie.0. Check for Q35 in
acpi_pcihp_disable_root_bus() to be able to forbid hot-plug using the
'acpi-root-pci-hotplug' flag.
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
---
hw/acpi/pcihp.c | 3 ++-
1 file changed, 2 insertions(+),
On Sun, May 23, 2021 at 10:26 AM Michael S. Tsirkin wrote:
>
> On Thu, May 13, 2021 at 08:26:35AM +0200, Julia Suvorova wrote:
> > The patch set consists of two parts:
> > patches 1-4: introduce new feature
> > 'acpi-pci-hotplug-with-bridge-support'
PCI Express does not allow hot-plug on pcie.0. Check for Q35 in
acpi_pcihp_disable_root_bus() to be able to forbid hot-plug using the
'acpi-root-pci-hotplug' flag.
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
---
hw/acpi/pcihp.c | 3 ++-
1 file changed, 2 insertions(+),
}
+
...
+Method (DVNT, 2, NotSerialized)
+{
+If ((Arg0 & One))
+{
+Notify (S00, Arg1)
+}
...
Signed-off-by: Julia Suvorova
---
tests/qtest/bios-tables-test-allowed-diff.h | 11 ---
tests/dat
All DSDT Q35 tables will be modified because ACPI hot-plug is enabled
by default.
Signed-off-by: Julia Suvorova
---
tests/qtest/bios-tables-test-allowed-diff.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables
-hotplug-with-bridge-support=off
Signed-off-by: Julia Suvorova
---
hw/acpi/ich9.c | 2 +-
hw/i386/pc.c | 4 +++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
index f6819c4f2a..e7b2cd9719 100644
--- a/hw/acpi/ich9.c
+++ b/hw/acpi/ich9.c
@@ -425,7
e 'hotplug=off' on the port means all hot-plug types are disabled.
Signed-off-by: Julia Suvorova
---
include/hw/boards.h | 1 +
hw/acpi/pcihp.c | 8
hw/core/machine.c | 19 +++
hw/i386/pc_q35.c| 8
hw/pci/pcie.c | 11 ++-
ed bridges
* use 'acpi-root-pci-hotplug'
* add migration states [Igor]
* minor style changes
v2:
* new ioport range for acpiphp [Gerd]
* drop find_pci_host() [Igor]
* explain magic numbers in _OSC [Igor]
* drop build_q35_pci_hotplug() wrapper [Igor]
Julia Suv
Implement notifications and gpe to support q35 ACPI PCI hot-plug.
Use 0xcc4 - 0xcd7 range for 'acpi-pci-hotplug' io ports.
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
---
hw/i386/acpi-build.h| 4
include/hw/acpi/ich9.h | 2 ++
include/hw/acpi/pcihp.h | 3 ++
Add acpi_pcihp to ich9_pm as part of
'acpi-pci-hotplug-with-bridge-support' option. Set default to false.
Signed-off-by: Julia Suvorova
---
hw/i386/acpi-build.h | 1 +
include/hw/acpi/ich9.h | 3 ++
hw/acpi/ich9.c | 68 ++
hw/ac
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/pci-host/i440fx.h | 2 +-
> include/hw/pci-host/pam.h| 2 ++
> include/hw/pci-host/q35.h| 2 +-
> hw/pci-host/pam.c| 2 +-
> hw/pci-host/q35.c| 2 +-
> 5 files changed, 6 insertio
On Sat, Nov 7, 2020 at 3:48 PM Philippe Mathieu-Daudé wrote:
>
> Hi, I am confuse with the LPC/GSI code.
>
> In pc_q35_init() we connect the LPC outputs to
> GSI input:
>
> 116 static void pc_q35_init(MachineState *machine)
> 117 {
> ...
> 240 /* irq lines */
> 241 gsi_state = pc_gsi_creat
On Wed, Oct 7, 2020 at 9:39 AM Stefano Garzarella wrote:
>
> On Tue, Oct 06, 2020 at 02:59:08PM +0200, Julia Suvorova wrote:
> > If devfn is assigned automatically, 'else' clauses will never be
> > executed. And if it does not matter for the reserved and availabl
'occupied' is spelled like 'ocuppied' in the message.
Signed-off-by: Julia Suvorova
---
hw/pci/pci.c | 2 +-
hw/ppc/spapr_pci.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 3c8f10b461..100c9381c2 100644
---
-device pcie-root-port,id=rp,.. \
-device pci-device,bus=rp
2. Add a new device to the same port:
device_add pci-device,bus=rp
The last command will add the device to slot 1 instead of
failing with "PCI: slot 0 function 0 already occupied..."
Signed-off-by: Julia Suvorov
On Thu, Oct 1, 2020 at 1:40 PM Michael S. Tsirkin wrote:
>
> On Thu, Oct 01, 2020 at 10:55:35AM +0200, Julia Suvorova wrote:
> > On Thu, Sep 24, 2020 at 11:20 AM Michael S. Tsirkin wrote:
> > >
> > > On Thu, Sep 24, 2020 at 09:00:06AM +0200, Julia Suvorova wrote:
1 - 100 of 293 matches
Mail list logo
