[RFC PATCH] migration/rdma: Remove qemu_rdma_broken_ipv6_kernel

2025-04-05 Thread Jack Wang
: Set RoCEv2 MGID according to spec 63a5f483af0e IB/cma: Set default gid type to RoCEv2 So remove the outdated function and it's usage. Cc: Peter Xu Cc: Li Zhijian Cc: Yu Zhang Cc: qemu-devel@nongnu.org Cc: linux-r...@vger.kernel.org Cc: mich...@flatgalaxy.com Signed-off-by

[PATCHv2] migration/rdma: Remove qemu_rdma_broken_ipv6_kernel

2025-04-01 Thread Jack Wang
I hit following error which testing migration in pure RoCE env: "-incoming rdma:[::]:8089: RDMA ERROR: You only have RoCE / iWARP devices in your systems and your management software has specified '[::]', but IPv6 over RoCE / iWARP is not supported in Linux.#012'." In our setup, we use rdma bind

[PATCH] migration/rdma: Remove qemu_rdma_broken_ipv6_kernel

2025-03-26 Thread Jack Wang
: Set RoCEv2 MGID according to spec 63a5f483af0e IB/cma: Set default gid type to RoCEv2 So remove the outdated function and it's usage. Cc: Peter Xu Cc: Li Zhijian Cc: Yu Zhang Cc: qemu-devel@nongnu.org Cc: linux-r...@vger.kernel.org Cc: mich...@flatgalaxy.com Signed-off-by: Jack Wang Tes

Questions about pci p2p

2024-07-24 Thread Hanjey Jack
Hello, I have 2 qemu questions: 1. Does qemu guest support pcie p2p through pice-switch if I passthrough 2 device which under the same physical pice-switch ? 2. If qemu can support, how can I config qemu cmdline ? Thanks.

[PATCH v3] memory tier: consolidate the initialization of memory tiers

2024-07-04 Thread Ho-Ren (Jack) Chuang
ng memory types"): [0/2] https://lkml.kernel.org/r/20240405000707.2670063-1-horenchu...@bytedance.com [1/2] https://lkml.kernel.org/r/20240405000707.2670063-2-horenchu...@bytedance.com [1/2] https://lkml.kernel.org/r/20240405000707.2670063-3-horenchu...@bytedance.com Signed-off-by: Ho-Ren

Re: [PATCH v2 1/1] memory tier: consolidate the initialization of memory tiers

2024-07-03 Thread Ho-Ren (Jack) Chuang
Hi Jonathan, I appreciate your feedback and valuable suggestions. Replies inlined. July 2, 2024 at 6:25 AM, "Jonathan Cameron" wrote: > > On Fri, 28 Jun 2024 06:09:23 +0000 > > "Ho-Ren (Jack) Chuang" wrote: > > > > > If we simply move t

Re: [PATCH v2 1/1] memory tier: consolidate the initialization of memory tiers

2024-07-01 Thread Ho-Ren (Jack) Chuang
Hi Huang, Ying, Thanks for your feedback and helpful suggestions. Replies inlined. June 30, 2024 at 10:13 PM, "Huang, Ying" wrote: > > Hi, Jack, > > "Ho-Ren (Jack) Chuang" writes: > > I suggest you to merge the [0/1] with the change log here. [0/1] &

[PATCH v2 1/1] memory tier: consolidate the initialization of memory tiers

2024-06-27 Thread Ho-Ren (Jack) Chuang
Ren (Jack) Chuang Suggested-by: Jonathan Cameron --- drivers/acpi/numa/hmat.c | 5 +-- include/linux/memory-tiers.h | 2 ++ mm/memory-tiers.c| 59 +++- 3 files changed, 28 insertions(+), 38 deletions(-) diff --git a/drivers/acpi/numa/hmat.

[PATCH v2 0/1] memory tier: consolidate the initialization of memory tiers

2024-06-27 Thread Ho-Ren (Jack) Chuang
0063-2-horenchu...@bytedance.com [1/2] https://lkml.kernel.org/r/20240405000707.2670063-3-horenchu...@bytedance.com Ho-Ren (Jack) Chuang (1): memory tier: consolidate the initialization of memory tiers drivers/acpi/numa/hmat.c | 5 +-- include/linux/memory-tiers.h | 2 ++ mm/memory-tiers.c

[PATCH v1] memory tier: consolidate the initialization of memory tiers

2024-06-20 Thread Ho-Ren (Jack) Chuang
Ren (Jack) Chuang --- Hi all, The current memory tier initialization process is distributed across two different functions, memory_tier_init() and memory_tier_late_init(). This design is hard to maintain. Thus, this patch is proposed to reduce the possible code paths by consolidating differ

Re: [External] Re: [PATCH v11 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-04-17 Thread Ho-Ren (Jack) Chuang
On Wed, Apr 10, 2024 at 9:51 AM Jonathan Cameron wrote: > > On Tue, 9 Apr 2024 12:02:31 -0700 > "Ho-Ren (Jack) Chuang" wrote: > > > Hi Jonathan, > > > > On Tue, Apr 9, 2024 at 9:12 AM Jonathan Cameron > > wrote: > > > > > > On Fr

Re: [External] Re: [PATCH v11 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-04-09 Thread Ho-Ren (Jack) Chuang
On Tue, Apr 9, 2024 at 7:33 PM Huang, Ying wrote: > > "Ho-Ren (Jack) Chuang" writes: > > > On Fri, Apr 5, 2024 at 7:03 AM Jonathan Cameron > > wrote: > >> > >> On Fri, 5 Apr 2024 00:07:06 + > >> "Ho-Ren (Jack) Chuang"

Re: [External] Re: [PATCH v11 1/2] memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types

2024-04-09 Thread Ho-Ren (Jack) Chuang
On Tue, Apr 9, 2024 at 2:50 PM Andrew Morton wrote: > > On Tue, 9 Apr 2024 12:00:06 -0700 "Ho-Ren (Jack) Chuang" > wrote: > > > Hi Jonathan, > > > > On Fri, Apr 5, 2024 at 6:56 AM Jonathan Cameron > > wrote: > > > > > > On Fri

Re: [External] Re: [PATCH v11 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-04-09 Thread Ho-Ren (Jack) Chuang
Hi Jonathan, On Tue, Apr 9, 2024 at 9:12 AM Jonathan Cameron wrote: > > On Fri, 5 Apr 2024 15:43:47 -0700 > "Ho-Ren (Jack) Chuang" wrote: > > > On Fri, Apr 5, 2024 at 7:03 AM Jonathan Cameron > > wrote: > > > > > > On Fri, 5 Apr 202

Re: [External] Re: [PATCH v11 1/2] memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types

2024-04-09 Thread Ho-Ren (Jack) Chuang
Hi Jonathan, On Fri, Apr 5, 2024 at 6:56 AM Jonathan Cameron wrote: > > On Fri, 5 Apr 2024 00:07:05 + > "Ho-Ren (Jack) Chuang" wrote: > > > Since different memory devices require finding, allocating, and putting > > memory types, these common

Re: [PATCH v11 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-04-05 Thread Ho-Ren (Jack) Chuang
On Fri, Apr 5, 2024 at 7:03 AM Jonathan Cameron wrote: > > On Fri, 5 Apr 2024 00:07:06 + > "Ho-Ren (Jack) Chuang" wrote: > > > The current implementation treats emulated memory devices, such as > > CXL1.1 type3 memory, as normal DRAM when

[PATCH v11 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-04-04 Thread Ho-Ren (Jack) Chuang
managed, a default memory type is created for storing all memory types that are not initialized by device drivers and as a fallback. Signed-off-by: Ho-Ren (Jack) Chuang Signed-off-by: Hao Xiang Reviewed-by: "Huang, Ying" --- mm/memory-ti

[PATCH v11 1/2] memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types

2024-04-04 Thread Ho-Ren (Jack) Chuang
Since different memory devices require finding, allocating, and putting memory types, these common steps are abstracted in this patch, enhancing the scalability and conciseness of the code. Signed-off-by: Ho-Ren (Jack) Chuang Reviewed-by: "Huang, Ying" --- drivers/dax/kmem.c

[PATCH v11 0/2] Improved Memory Tier Creation for CPUless NUMA Nodes

2024-04-04 Thread Ho-Ren (Jack) Chuang
* https://lore.kernel.org/lkml/20240312061729.1997111-1-horenchu...@bytedance.com/T/#u -v1: * https://lore.kernel.org/lkml/20240301082248.3456086-1-horenchu...@bytedance.com/T/#u Ho-Ren (Jack) Chuang (2): memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and pu

Re: [External] Re: [PATCH v10 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-04-04 Thread Ho-Ren (Jack) Chuang
nice per character > ruler at the top of the window. > > I wonder if you have a different tab indent size? The kernel uses 8 > characters. It might explain the few other odd indents if perhaps > you have it at 4 in your editor? > > https://www.kernel.org/doc/html/v4.10/process/coding-style.html > Got it. I was using tab=4. I will change to 8. Thanks! > Jonathan > > > > > > > + * initialized. > > > > + */ > > > > + continue; > > > > + > > > > memtier = set_node_memory_tier(node); > > > > if (IS_ERR(memtier)) > > > > /* > > > > > > > > -- Best regards, Ho-Ren (Jack) Chuang 莊賀任

Re: [PATCH v10 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-04-03 Thread Ho-Ren (Jack) Chuang
ers with smaller adistance > >* than default DRAM tier. > >*/ > > - default_dram_type = alloc_memory_type(MEMTIER_ADISTANCE_DRAM); > > + default_dram_type = mt_find_alloc_memory_type(MEMTIER_ADISTANCE_DRAM, > > + > > &default_memory_types); > > Unusual indenting. Align with just after ( > Aligning with "(" will exceed 100 columns. Would that be acceptable? > > if (IS_ERR(default_dram_type)) > > panic("%s() failed to allocate default DRAM tier\n", > > __func__); > > > > @@ -868,6 +921,14 @@ static int __init memory_tier_init(void) > >* types assigned. > >*/ > > for_each_node_state(node, N_MEMORY) { > > + if (!node_state(node, N_CPU)) > > + /* > > + * Defer memory tier initialization on CPUless numa > > nodes. > > + * These will be initialized after firmware and > > devices are > > I think this wraps at just over 80 chars. Seems silly to wrap so tightly and > not > quite fit under 80. (this is about 83 chars. > I can fix this. I have a question. From my patch, this is <80 chars. However, in an email, this is >80 chars. Does that mean we need to count the number of chars in an email, not in a patch? Or if I missed something? like vim configuration or? > > + * initialized. > > + */ > > + continue; > > + > > memtier = set_node_memory_tier(node); > > if (IS_ERR(memtier)) > > /* > -- Best regards, Ho-Ren (Jack) Chuang 莊賀任

Re: [PATCH v10 1/2] memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types

2024-04-03 Thread Ho-Ren (Jack) Chuang
Hi Jonathan, Thanks for your feedback. I will fix them (inlined) in the next V11. No worries, it's never too late! On Wed, Apr 3, 2024 at 9:52 AM Jonathan Cameron wrote: > > On Tue, 2 Apr 2024 00:17:37 + > "Ho-Ren (Jack) Chuang" wrote: > > > Since differe

[PATCH v10 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-04-01 Thread Ho-Ren (Jack) Chuang
managed, a default memory type is created for storing all memory types that are not initialized by device drivers and as a fallback. Signed-off-by: Ho-Ren (Jack) Chuang Signed-off-by: Hao Xiang Reviewed-by: "Huang, Ying" --- include/linux/memory-tiers.h | 5 +- mm/memo

[PATCH v10 1/2] memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types

2024-04-01 Thread Ho-Ren (Jack) Chuang
Since different memory devices require finding, allocating, and putting memory types, these common steps are abstracted in this patch, enhancing the scalability and conciseness of the code. Signed-off-by: Ho-Ren (Jack) Chuang Reviewed-by: "Huang, Ying" --- drivers/dax/kmem.c

[PATCH v10 0/2] Improved Memory Tier Creation for CPUless NUMA Nodes

2024-04-01 Thread Ho-Ren (Jack) Chuang
40312061729.1997111-1-horenchu...@bytedance.com/T/#u -v1: * https://lore.kernel.org/lkml/20240301082248.3456086-1-horenchu...@bytedance.com/T/#u Ho-Ren (Jack) Chuang (2): memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types memory tier: create

Re: [External] Re: [PATCH v9 1/2] memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types

2024-04-01 Thread Ho-Ren (Jack) Chuang
Hi SeongJae, On Mon, Apr 1, 2024 at 11:27 AM Ho-Ren (Jack) Chuang wrote: > > Hi SeongJae, > > On Sun, Mar 31, 2024 at 12:09 PM SeongJae Park wrote: > > > > Hi Ho-Ren, > > > > On Fri, 29 Mar 2024 05:33:52 + "Ho-Ren (Jack) Chuang" > > wro

Re: [External] Re: [PATCH v9 1/2] memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types

2024-04-01 Thread Ho-Ren (Jack) Chuang
Hi SeongJae, On Sun, Mar 31, 2024 at 12:09 PM SeongJae Park wrote: > > Hi Ho-Ren, > > On Fri, 29 Mar 2024 05:33:52 +0000 "Ho-Ren (Jack) Chuang" > wrote: > > > Since different memory devices require finding, allocating, and putting > > memory types, t

[PATCH v9 1/2] memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types

2024-03-28 Thread Ho-Ren (Jack) Chuang
Since different memory devices require finding, allocating, and putting memory types, these common steps are abstracted in this patch, enhancing the scalability and conciseness of the code. Signed-off-by: Ho-Ren (Jack) Chuang Reviewed-by: "Huang, Ying" --- drivers/dax/kmem.c

[PATCH v9 0/2] Improved Memory Tier Creation for CPUless NUMA Nodes

2024-03-28 Thread Ho-Ren (Jack) Chuang
://lore.kernel.org/lkml/20240312061729.1997111-1-horenchu...@bytedance.com/T/#u -v1: * https://lore.kernel.org/lkml/20240301082248.3456086-1-horenchu...@bytedance.com/T/#u Ho-Ren (Jack) Chuang (2): memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types memo

[PATCH v9 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-03-28 Thread Ho-Ren (Jack) Chuang
managed, a default memory type is created for storing all memory types that are not initialized by device drivers and as a fallback. Signed-off-by: Ho-Ren (Jack) Chuang Signed-off-by: Hao Xiang Reviewed-by: "Huang, Ying" --- mm/memory-ti

Re: [External] Re: [PATCH v8 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-03-28 Thread Ho-Ren (Jack) Chuang
On Thu, Mar 28, 2024 at 5:59 PM Huang, Ying wrote: > > "Ho-Ren (Jack) Chuang" writes: > > > The current implementation treats emulated memory devices, such as > > CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory > > (E820_TYPE_RAM).

[PATCH v8 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-03-28 Thread Ho-Ren (Jack) Chuang
managed, a default memory type is created for storing all memory types that are not initialized by device drivers and as a fallback. Signed-off-by: Ho-Ren (Jack) Chuang Signed-off-by: Hao Xiang Reviewed-by: "Huang, Ying" --- mm/memory-ti

[PATCH v8 1/2] memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types

2024-03-28 Thread Ho-Ren (Jack) Chuang
Since different memory devices require finding, allocating, and putting memory types, these common steps are abstracted in this patch, enhancing the scalability and conciseness of the code. Signed-off-by: Ho-Ren (Jack) Chuang Reviewed-by: "Huang, Ying" --- drivers/dax/kmem.c

[PATCH v8 0/2] Improved Memory Tier Creation for CPUless NUMA Nodes

2024-03-28 Thread Ho-Ren (Jack) Chuang
c_memory_type() * Use the expected way to use set_node_memory_tier instead of modifying it * https://lore.kernel.org/lkml/20240312061729.1997111-1-horenchu...@bytedance.com/T/#u -v1: * https://lore.kernel.org/lkml/20240301082248.3456086-1-horenchu...@bytedance.com/T/#u Ho-Ren (Jack) Chuang

[PATCH v7 0/2] Improved Memory Tier Creation for CPUless NUMA Nodes

2024-03-28 Thread Ho-Ren (Jack) Chuang
e expected way to use set_node_memory_tier instead of modifying it * https://lore.kernel.org/lkml/20240312061729.1997111-1-horenchu...@bytedance.com/T/#u -v1: * https://lore.kernel.org/lkml/20240301082248.3456086-1-horenchu...@bytedance.com/T/#u Ho-Ren (Jack) Chuang (2): memory tier: dax/kme

Re: [External] Re: [PATCH v6 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-03-28 Thread Ho-Ren (Jack) Chuang
On Wed, Mar 27, 2024 at 6:37 PM Huang, Ying wrote: > > "Ho-Ren (Jack) Chuang" writes: > > [snip] > > > @@ -655,6 +672,34 @@ void mt_put_memory_types(struct list_head > > *memory_types) > > } > > EXPORT_SYMBOL_GPL(mt_put_memory_types); >

[PATCH v6 1/2] memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types

2024-03-27 Thread Ho-Ren (Jack) Chuang
Since different memory devices require finding, allocating, and putting memory types, these common steps are abstracted in this patch, enhancing the scalability and conciseness of the code. Signed-off-by: Ho-Ren (Jack) Chuang --- drivers/dax/kmem.c | 20 ++-- include

[PATCH v6 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-03-27 Thread Ho-Ren (Jack) Chuang
managed, a default memory type is created for storing all memory types that are not initialized by device drivers and as a fallback. Signed-off-by: Ho-Ren (Jack) Chuang Signed-off-by: Hao Xiang --- mm/memory-tiers.c | 94 +++ 1 file changed, 78

[PATCH v6 0/2] Improved Memory Tier Creation for CPUless NUMA Nodes

2024-03-27 Thread Ho-Ren (Jack) Chuang
97111-1-horenchu...@bytedance.com/T/#u -v1: * https://lore.kernel.org/lkml/20240301082248.3456086-1-horenchu...@bytedance.com/T/#u Ho-Ren (Jack) Chuang (2): memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types memory tier: create CPUless memory tie

Re: [External] Re: [PATCH v5 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-03-26 Thread Ho-Ren (Jack) Chuang
On Tue, Mar 26, 2024 at 10:52 PM Huang, Ying wrote: > > "Ho-Ren (Jack) Chuang" writes: > > > The current implementation treats emulated memory devices, such as > > CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory > > (E820_TYPE_

[PATCH v5 1/2] memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types

2024-03-26 Thread Ho-Ren (Jack) Chuang
Since different memory devices require finding, allocating, and putting memory types, these common steps are abstracted in this patch, enhancing the scalability and conciseness of the code. Signed-off-by: Ho-Ren (Jack) Chuang --- drivers/dax/kmem.c | 20 ++-- include

[PATCH v5 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-03-26 Thread Ho-Ren (Jack) Chuang
` Because an error path was not handled properly in `mt_perf_to_adistance`, unlock before returning the error. Signed-off-by: Ho-Ren (Jack) Chuang Signed-off-by: Hao Xiang --- mm/memory-tiers.c | 85 +++ 1 file changed, 72 insertions(+), 13 deletions

[PATCH v5 0/2] Improved Memory Tier Creation for CPUless NUMA Nodes

2024-03-26 Thread Ho-Ren (Jack) Chuang
g it * https://lore.kernel.org/lkml/20240312061729.1997111-1-horenchu...@bytedance.com/T/#u -v1: * https://lore.kernel.org/lkml/20240301082248.3456086-1-horenchu...@bytedance.com/T/#u Ho-Ren (Jack) Chuang (2): memory tier: dax/kmem: introduce an abstract layer for finding, allocating, a

Re: [External] Re: [PATCH v4 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-03-25 Thread Ho-Ren (Jack) Chuang
On Mon, Mar 25, 2024 at 8:08 PM Huang, Ying wrote: > > "Ho-Ren (Jack) Chuang" writes: > > > On Fri, Mar 22, 2024 at 1:41 AM Huang, Ying wrote: > >> > >> "Ho-Ren (Jack) Chuang" writes: > >> > >> > The current implementat

Re: [External] Re: [PATCH v4 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-03-22 Thread Ho-Ren (Jack) Chuang
On Fri, Mar 22, 2024 at 1:41 AM Huang, Ying wrote: > > "Ho-Ren (Jack) Chuang" writes: > > > The current implementation treats emulated memory devices, such as > > CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory > > (E820_TYPE_RAM).

[PATCH v4 0/2] Improved Memory Tier Creation for CPUless NUMA Nodes

2024-03-22 Thread Ho-Ren (Jack) Chuang
ml/20240312061729.1997111-1-horenchu...@bytedance.com/T/#u -v1: * https://lore.kernel.org/lkml/20240301082248.3456086-1-horenchu...@bytedance.com/T/#u Ho-Ren (Jack) Chuang (2): memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types memory tier:

[PATCH v4 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-03-22 Thread Ho-Ren (Jack) Chuang
managed, a default memory type is created for storing all memory types that are not initialized by device drivers and as a fallback. Signed-off-by: Ho-Ren (Jack) Chuang Signed-off-by: Hao Xiang --- mm/memory-tiers.c | 73 --- 1 file changed, 63

[PATCH v4 1/2] memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types

2024-03-22 Thread Ho-Ren (Jack) Chuang
Since different memory devices require finding, allocating, and putting memory types, these common steps are abstracted in this patch, enhancing the scalability and conciseness of the code. Signed-off-by: Ho-Ren (Jack) Chuang --- drivers/dax/kmem.c | 20 ++-- include

Re: [External] Re: [PATCH v3 1/2] memory tier: dax/kmem: create CPUless memory tiers after obtaining HMAT info

2024-03-20 Thread Ho-Ren (Jack) Chuang
On Wed, Mar 20, 2024 at 12:15 AM Huang, Ying wrote: > > "Ho-Ren (Jack) Chuang" writes: > > > The current implementation treats emulated memory devices, such as > > CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory > > (E820_TYPE_

[PATCH v3 1/2] memory tier: dax/kmem: create CPUless memory tiers after obtaining HMAT info

2024-03-19 Thread Ho-Ren (Jack) Chuang
type is created for storing all memory types that are not initialized by device drivers and as a fallback. Signed-off-by: Ho-Ren (Jack) Chuang Signed-off-by: Hao Xiang --- drivers/dax/kmem.c | 13 + include/linux/memory-tiers.h | 7 +++ mm/memory-tiers.c| 94

[PATCH v3 2/2] memory tier: dax/kmem: abstract memory types put

2024-03-19 Thread Ho-Ren (Jack) Chuang
Abstract `kmem_put_memory_types()` into `mt_put_memory_types()` to accommodate various memory types and enhance flexibility, similar to `mt_find_alloc_memory_type()`. Signed-off-by: Ho-Ren (Jack) Chuang --- drivers/dax/kmem.c | 7 +-- include/linux/memory-tiers.h | 6 ++ mm

[PATCH v3 0/2] Improved Memory Tier Creation for CPUless NUMA Nodes

2024-03-19 Thread Ho-Ren (Jack) Chuang
() * Use the expected way to use set_node_memory_tier instead of modifying it * https://lore.kernel.org/lkml/20240312061729.1997111-1-horenchu...@bytedance.com/T/#u -v1: * https://lore.kernel.org/lkml/20240301082248.3456086-1-horenchu...@bytedance.com/T/#u Ho-Ren (Jack) Chuang (2): memory

Re: [External] Re: [PATCH v2 1/1] memory tier: acpi/hmat: create CPUless memory tiers after obtaining HMAT info

2024-03-18 Thread Ho-Ren (Jack) Chuang
I'm working on V3. Thanks for Ying's feedback. cc: sthanne...@micron.com On Thu, Mar 14, 2024 at 12:54 AM Huang, Ying wrote: > > "Ho-Ren (Jack) Chuang" writes: > > > On Tue, Mar 12, 2024 at 2:21 AM Huang, Ying wrote: > >> > >> &q

Re: [External] Re: [PATCH v2 1/1] memory tier: acpi/hmat: create CPUless memory tiers after obtaining HMAT info

2024-03-13 Thread Ho-Ren (Jack) Chuang
On Tue, Mar 12, 2024 at 2:21 AM Huang, Ying wrote: > > "Ho-Ren (Jack) Chuang" writes: > > > The current implementation treats emulated memory devices, such as > > CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory > > (E820_TYPE_RAM).

[PATCH v2 1/1] memory tier: acpi/hmat: create CPUless memory tiers after obtaining HMAT info

2024-03-11 Thread Ho-Ren (Jack) Chuang
but also prevents holding a large lock simultaneously. Signed-off-by: Ho-Ren (Jack) Chuang Signed-off-by: Hao Xiang --- drivers/acpi/numa/hmat.c | 11 ++ drivers/dax/kmem.c | 13 +-- include/linux/acpi.h | 6 include/linux/memory-tiers.h | 8 + mm/memory

[PATCH v2 0/1] Improved Memory Tier Creation for CPUless NUMA Nodes

2024-03-11 Thread Ho-Ren (Jack) Chuang
y_tier instead of modifying it -v1: * https://lore.kernel.org/linux-mm/20240301082248.3456086-1-horenchu...@bytedance.com/T/ Ho-Ren (Jack) Chuang (1): memory tier: acpi/hmat: create CPUless memory tiers after obtaining HMAT info drivers/acpi/numa/hmat.c | 11 ++ drivers/dax/kmem.c

Re: [External] Re: [PATCH v1 1/1] memory tier: acpi/hmat: create CPUless memory tiers after obtaining HMAT info

2024-03-05 Thread Ho-Ren (Jack) Chuang
On Tue, Mar 5, 2024 at 6:27 PM Huang, Ying wrote: > > "Ho-Ren (Jack) Chuang" writes: > > > On Sun, Mar 3, 2024 at 6:42 PM Huang, Ying wrote: > >> > >> Hi, Jack, > >> > >> "Ho-Ren (Jack) Chuang" writes: > >> > &g

Re: [External] Re: [PATCH v1 1/1] memory tier: acpi/hmat: create CPUless memory tiers after obtaining HMAT info

2024-03-05 Thread Ho-Ren (Jack) Chuang
On Sun, Mar 3, 2024 at 6:42 PM Huang, Ying wrote: > > Hi, Jack, > > "Ho-Ren (Jack) Chuang" writes: > > > * Introduce `mt_init_with_hmat()` > > We defer memory tier initialization for those CPUless NUMA nodes > > until acquiring HMAT info. `mt_init_wi

Re: [External] Re: [PATCH v1 0/1] Improved Memory Tier Creation for CPUless NUMA Nodes

2024-03-04 Thread Ho-Ren (Jack) Chuang
On Mon, Mar 4, 2024 at 10:36 PM Huang, Ying wrote: > > "Ho-Ren (Jack) Chuang" writes: > > > On Sun, Mar 3, 2024 at 6:47 PM Huang, Ying wrote: > >> > >> "Ho-Ren (Jack) Chuang" writes: > >> > >> > The memory tiering com

Re: [External] Re: [PATCH v1 0/1] Improved Memory Tier Creation for CPUless NUMA Nodes

2024-03-04 Thread Ho-Ren (Jack) Chuang
On Sun, Mar 3, 2024 at 6:47 PM Huang, Ying wrote: > > "Ho-Ren (Jack) Chuang" writes: > > > The memory tiering component in the kernel is functionally useless for > > CPUless memory/non-DRAM devices like CXL1.1 type3 memory because the nodes > > are lumped

Re: [External] Re: [PATCH v1 0/1] Improved Memory Tier Creation for CPUless NUMA Nodes

2024-03-04 Thread Ho-Ren (Jack) Chuang
On Sun, Mar 3, 2024 at 6:47 PM Huang, Ying wrote: > > "Ho-Ren (Jack) Chuang" writes: > > > The memory tiering component in the kernel is functionally useless for > > CPUless memory/non-DRAM devices like CXL1.1 type3 memory because the nodes > > are lumped

[PATCH v1 1/1] memory tier: acpi/hmat: create CPUless memory tiers after obtaining HMAT info

2024-03-01 Thread Ho-Ren (Jack) Chuang
holding a large lock simultaneously. Signed-off-by: Ho-Ren (Jack) Chuang Signed-off-by: Hao Xiang --- drivers/acpi/numa/hmat.c | 3 ++ include/linux/memory-tiers.h | 6 +++ mm/memory-tiers.c| 76 3 files changed, 77 insertions(+), 8 deletions

[PATCH v1 0/1] Improved Memory Tier Creation for CPUless NUMA Nodes

2024-03-01 Thread Ho-Ren (Jack) Chuang
correct memory tiering for the memory nodes. Ho-Ren (Jack) Chuang (1): memory tier: acpi/hmat: create CPUless memory tiers after obtaining HMAT info drivers/acpi/numa/hmat.c | 3 ++ include/linux/memory-tiers.h | 6 +++ mm/memory-tiers.c| 76

[QEMU-devel][RFC PATCH 1/1] backends/hostmem: qapi/qom: Add an ObjectOption for memory-backend-* called HostMemType and its arg 'cxlram'

2023-12-31 Thread Ho-Ren (Jack) Chuang
tile-memdev=vmem0,id=cxl-vmem0 \ -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=19G,cxl-fmw.0.interleave-granularity=8k \ In v1, we plan to move most of the implementations to util and break down this patch into different smaller patches. Signed-off-by: Ho-Ren (Jack) Chuang Signed-off-by: Hao

[PATCH] doc: Adapt example to for numa setting.

2022-04-28 Thread Jack Wang
Add numa sgx setting in one leftover example, without numa setting qemu will error out with message below: qemu-7.0: Parameter 'sgx-epc.0.node' is missing Fixes: d1889b36098c ("doc: Add the SGX numa description") Cc: Yu Zhang Signed-off-by: Jack Wang --- docs/system/i386/sg

[PATCH v3] migration/rdma: set the REUSEADDR option for destination

2022-02-17 Thread Jack Wang
number. Set the REUSEADDR option for destination, This allow address could be reused to avoid rdma_bind_addr error out. Signed-off-by: Jack Wang Reviewed-by: Pankaj Gupta --- v3: add reviewed-by tags from David and Pankaj. v2: extend commit message as discussed with Pankaj and David

[PATCH v2] migration/rdma: set the REUSEADDR option for destination

2022-02-08 Thread Jack Wang
number. Set the REUSEADDR option for destination, This allow address could be reused to avoid rdma_bind_addr error out. Signed-off-by: Jack Wang --- v2: extend commit message as discussed with Pankaj and David --- migration/rdma.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a

[PATCH 1/2] migration/rdma: Increase the backlog from 5 to 128

2022-02-01 Thread Jack Wang
So it can handle more incoming requests. Signed-off-by: Jack Wang --- migration/rdma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/migration/rdma.c b/migration/rdma.c index c7c7a384875b..2e223170d06d 100644 --- a/migration/rdma.c +++ b/migration/rdma.c @@ -4238,7 +4238,7

[PATCH 2/2] migration/rdma: set the REUSEADDR option for destination

2022-02-01 Thread Jack Wang
This allow address could be reused to avoid rdma_bind_addr error out. Signed-off-by: Jack Wang --- migration/rdma.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/migration/rdma.c b/migration/rdma.c index 2e223170d06d..b498ef013c77 100644 --- a/migration/rdma.c +++ b/migration

Re: Property '.hmat' not found

2020-11-18 Thread Jack Kuo
r customizing CPU cache, and now I find that I'm wrong... It's for memory side cache. Thank you very much, really help me a lot. Sincerely, Jack Eduardo Habkost 於 2020年11月17日 週二 下午11:09寫道: > On Tue, Nov 17, 2020 at 11:49:38AM +0800, 郭俊甫 (Jack Kuo) wrote: > > > > >

Re: Property '.hmat' not found

2020-11-17 Thread Jack Kuo
` [1] https://wiki.qemu.org/Hosts/Linux#Building_QEMU_for_Linux Sincerely, Jack Eduardo Habkost 於 2020年11月17日 週二 上午3:02寫道: > On Mon, Nov 16, 2020 at 01:51:37PM +0100, Philippe Mathieu-Daudé wrote: > > Cc'ing Igor & Eduardo. > > Thanks! > > > > > On 11/13/20 1

Re: io_uring possibly the culprit for qemu hang (linux-5.4.y)

2020-10-01 Thread Jack Wang
Stefano Garzarella 于2020年10月1日周四 上午10:59写道: > > +Cc: qemu-devel@nongnu.org > > Hi, > > On Thu, Oct 01, 2020 at 01:26:51AM +0900, Ju Hyung Park wrote: > > Hi everyone. > > > > I have recently switched to a setup running QEMU 5.0(which supports > > io_uring) for a Windows 10 guest on Linux v5.4.63.

Re: [PATCH 3/3] target/i386: modify Icelake-Client and Icelake-Server CPU model number

2020-02-27 Thread Jack Wang
Chenyi Qiang 于2020年2月27日周四 上午10:07写道: > > According to the Intel Icelake family list, Icelake-Client uses model > number 126(0x7D) 0x7D is 125 in hex, so the commit message needs to be fixed. Cheers Jack Wang

Re: [Qemu-devel] Overcommiting cpu results in all vms offline

2018-09-17 Thread Jack Wang
Stefan Priebe - Profihost AG 于2018年9月17日周一 上午9:00写道: > > Hi, > > Am 17.09.2018 um 08:38 schrieb Jack Wang: > > Stefan Priebe - Profihost AG 于2018年9月16日周日 下午3:31写道: > >> > >> Hello, > >> > >> while overcommiting cpu I had several situations wh

Re: [Qemu-devel] Overcommiting cpu results in all vms offline

2018-09-16 Thread Jack Wang
ogs when all VMs go offline? Maybe OOMkiller play a role there? Regards, Jack

[Qemu-devel] [PATCH 0/1] multiboot.c: Document as fixed against CVE-2018-7550

2018-03-21 Thread Jack Schwartz
ple may get confused when they see different fixes associated with the same CVE. Thanks, Jack Jack Schwartz (1): multiboot.c: Document as fixed against CVE-2018-7550 -- 1.8.3.1

[Qemu-devel] [PATCH 1/1] multiboot.c: Document as fixed against CVE-2018-7550

2018-03-21 Thread Jack Schwartz
This empty commit documents multiboot.c as fixed against CVE-2018-7550. The fix, dated Dec 21 2017, went in before the CVE was created, as: 2a8fcd119eb7 ("multiboot: bss_end_addr can be zero") Fixes: CVE-2018-7550 Signed-off-by: Jack Schwartz Reviewed-by: Mark Kanda -- 1.8.3.1

Re: [Qemu-devel] [PATCH 1/5] multiboot: Reject kernels exceeding the address space

2018-03-15 Thread Jack Schwartz
On 03/15/18 10:18, Kevin Wolf wrote: Am 15.03.2018 um 17:55 hat Jack Schwartz geschrieben: On 03/15/18 08:54, Kevin Wolf wrote: Am 15.03.2018 um 06:19 hat Jack Schwartz geschrieben: Hi Kevin. My comments are inline... On 2018-03-14 10:32, Kevin Wolf wrote: The code path with a manually set

Re: [Qemu-devel] [PATCH 1/5] multiboot: Reject kernels exceeding the address space

2018-03-15 Thread Jack Schwartz
On 03/15/18 08:54, Kevin Wolf wrote: Am 15.03.2018 um 06:19 hat Jack Schwartz geschrieben: Hi Kevin. My comments are inline... On 2018-03-14 10:32, Kevin Wolf wrote: The code path with a manually set mh_load_addr in the Multiboot header checks that load_end_addr <= load_addr, but the p

Re: [Qemu-devel] [PATCH 1/5] multiboot: Reject kernels exceeding the address space

2018-03-14 Thread Jack Schwartz
s fine. Modulo above comments:     Reviewed-by: Jack Schwartz     Thanks,     Jack Signed-off-by: Kevin Wolf --- hw/i386/multiboot.c | 4 1 file changed, 4 insertions(+) diff --git a/hw/i386/multiboot.c b/hw/i386/multiboot.c index b9064264d8..1e215bf8d3 100644 --- a/hw/i386/multiboot.c ++

Re: [Qemu-devel] [PATCH 0/5] multiboot: Fix buffer overflow on invalid kernels

2018-03-14 Thread Jack Schwartz
Hi Kevin. I see an issue with the commit message of patch 1; please see my reply to that patch for details.  I fully understand patches 1,2,3, patch 4 except for some of the Makefile black magic, and patch 5 looks reasonable to me. So, for patches 2,3,4,5:     Reviewed-by: Jack Schwartz

Re: [Qemu-devel] [PATCH QEMU v1 0/4] multiboot: bss_end_addr can be zero / cleanup

2018-03-06 Thread Jack Schwartz
Hi Kevin and everyone. On 2018-03-05 00:13, Kevin Wolf wrote: Am 02.03.2018 um 20:32 hat Jack Schwartz geschrieben: Hi Kevin. On 2018-01-15 07:54, Kevin Wolf wrote: Am 21.12.2017 um 18:25 hat Jack Schwartz geschrieben: Properly account for the possibility of multiboot kernels with a zero

Re: [Qemu-devel] [PATCH] multiboot: check mh_load_end_addr address field

2018-03-06 Thread Jack Schwartz
, but they got delayed.  However, I will be re-sending updated patches out later today.  Please stay tuned...     Thanks,     Jack On 02/27/18 11:48, P J P wrote: From: Prasad J Pandit While loading kernel via multiboot-v1 image, (flags & 0x0001) indicates that multiboot header cont

Re: [Qemu-devel] [PATCH QEMU v1 0/4] multiboot: bss_end_addr can be zero / cleanup

2018-03-02 Thread Jack Schwartz
Hi Kevin. On 2018-01-15 07:54, Kevin Wolf wrote: Am 21.12.2017 um 18:25 hat Jack Schwartz geschrieben: Properly account for the possibility of multiboot kernels with a zero bss_end_addr. The Multiboot Specification, section 3.1.3 allows for kernels without a bss section, by allowing a zeroed

Re: [Qemu-devel] [PATCH 1/4] multiboot: Change multiboot_info from array of bytes to a C struct

2018-02-06 Thread Jack Schwartz
Hi Anatol and Kevin. Kevin and Anatol, thanks for your replies. A few comments inline close to the bottom... On 2018-02-05 13:43, Anatol Pomozov wrote: Hi On Wed, Jan 31, 2018 at 1:12 AM, Kevin Wolf wrote: Am 31.01.2018 um 00:15 hat Jack Schwartz geschrieben: Hi Anatol and Kevin. Even

Re: [Qemu-devel] vhost-user question

2018-02-01 Thread jack
that is what i really want to know,thanks very very much!!! from jack chen On 2/1/2018 18:30,[1]Dr. David Alan Gilbert wrote: * jack.chen (zhun...@gmail.com) wrote: > Thanks,But my question is how the fd belonging to qemu can be used in > another process s

Re: [Qemu-devel] [PATCH 1/4] multiboot: Change multiboot_info from array of bytes to a C struct

2018-01-30 Thread Jack Schwartz
entry->base_addr, - entry->base_addr + entry->length, + entry->addr, + entry->addr + entry->len, entry->type, entry->size); } diff --git a/tests/multiboot/modules.c b/tests/multiboot

Re: [Qemu-devel] [PATCH 2/4] multiboot: load elf sections and section headers

2018-01-30 Thread Jack Schwartz
FLAGS 0x2 #define MB_CHECKSUM -(MB_MAGIC + MB_FLAGS) C headers can be included in assembly files.  Since you are bringing over multiboot_header.h, why not include it and use its values instead of re-defining them here?     Thanks,     Jack .align 4

Re: [Qemu-devel] [PATCH QEMU v1 0/4] multiboot: bss_end_addr can be zero / cleanup

2018-01-19 Thread Jack Schwartz
Hi Anatol, Daniel and Kevin. On 01/19/18 10:36, Anatol Pomozov wrote: Hello Jack On Wed, Jan 17, 2018 at 12:06 PM, Jack Schwartz wrote: Hi Kevin and Anatol. Kevin, thanks for your review. More inline below... On 01/15/18 07:54, Kevin Wolf wrote: Am 21.12.2017 um 18:25 hat Jack Schwartz

Re: [Qemu-devel] [PATCH QEMU v1 0/4] multiboot: bss_end_addr can be zero / cleanup

2018-01-17 Thread Jack Schwartz
Hi Kevin and Anatol. Kevin, thanks for your review. More inline below... On 01/15/18 07:54, Kevin Wolf wrote: Am 21.12.2017 um 18:25 hat Jack Schwartz geschrieben: Properly account for the possibility of multiboot kernels with a zero bss_end_addr. The Multiboot Specification, section 3.1.3

[Qemu-devel] ping: Re: [PATCH QEMU v1 0/4] multiboot: bss_end_addr can be zero / cleanup

2018-01-12 Thread Jack Schwartz
://patchwork.ozlabs.org/patch/852046/ 4/4 multiboot: fprintf(stderr...) -> error_report() http://patchwork.ozlabs.org/patch/852051/     Thanks,     Jack On 12/21/17 09:25, Jack Schwartz wrote: Properly account for the possibility of multiboot kernels with a zero bss_end_addr. The Multib

Re: [Qemu-devel] [PATCH v1 1/1] block: Add numeric errno field to BLOCK_IO_ERROR events

2018-01-10 Thread Jack Schwartz
Hi Kevin. Thanks for your feedback. Looks like my team's project plans have changed, and there is no need to pursue this further.  We can work with the existing reason string.     Thanks,     Jack On 01/09/18 02:24, Kevin Wolf wrote: Am 08.01.2018 um 20:57 hat Jack Sch

Re: [Qemu-devel] [PATCH v1 1/1] block: Add numeric errno field to BLOCK_IO_ERROR events

2018-01-08 Thread Jack Schwartz
Hi Kevin. On 2017-12-22 05:52, Kevin Wolf wrote: Am 22.12.2017 um 01:11 hat Jack Schwartz geschrieben: BLOCK_IO_ERROR events currently contain a "reason" string which is strerror(errno) of the error. This enhancement provides those events with the numeric errno value as well, s

[Qemu-devel] [PATCH v1 1/1] block: Add numeric errno field to BLOCK_IO_ERROR events

2017-12-21 Thread Jack Schwartz
BLOCK_IO_ERROR events currently contain a "reason" string which is strerror(errno) of the error. This enhancement provides those events with the numeric errno value as well, since it is easier to parse for error type than a string. Signed-off-by: Jack Schwartz Reviewed-by: Konrad Rzes

[Qemu-devel] [PATCH v1 0/1] block: Add numeric errno field to BLOCK_IO_ERROR events

2017-12-21 Thread Jack Schwartz
s. That file's prior reference to errno confirms that Windows will work with the code change. - If there would be a Linux vs Windows difference in mapping of errno to error string values, that difference would have been in place before my changes. Thanks, Jack Jack Schwartz (1): block: Add numeric errno field to BLOCK_IO_ERROR events block/block-backend.c | 2 +- qapi/block-core.json | 12 ++-- 2 files changed, 11 insertions(+), 3 deletions(-) -- 1.8.3.1

[Qemu-devel] [PATCH QEMU v1 4/4] multiboot: fprintf(stderr...) -> error_report()

2017-12-21 Thread Jack Schwartz
Change all fprintf(stderr...) calls in hw/i386/multiboot.c to call error_report() instead, including the mb_debug macro. Remove the "\n" from strings passed to all modified calls, since error_report() appends one. Signed-off-by: Jack Schwartz Reviewed-by: Daniel Kiper --- hw/i386/m

[Qemu-devel] [PATCH QEMU v1 1/4] multiboot: bss_end_addr can be zero

2017-12-21 Thread Jack Schwartz
The multiboot spec (https://www.gnu.org/software/grub/manual/multiboot/), section 3.1.3, allows for bss_end_addr to be zero. A zero bss_end_addr signifies there is no .bss section. Suggested-by: Daniel Kiper Signed-off-by: Jack Schwartz Reviewed-by: Daniel Kiper --- hw/i386/multiboot.c | 18

[Qemu-devel] [PATCH QEMU v1 0/4] multiboot: bss_end_addr can be zero / cleanup

2017-12-21 Thread Jack Schwartz
repo for two months. Thanks, Jack Jack Schwartz (4): multiboot: bss_end_addr can be zero multiboot: Remove unused variables from multiboot.c multiboot: Use header names when displaying fields multiboot: fprintf(stderr...) -> error_report() h

[Qemu-devel] [PATCH QEMU v1 3/4] multiboot: Use header names when displaying fields

2017-12-21 Thread Jack Schwartz
Refer to field names when displaying fields in printf and debug statements. Signed-off-by: Jack Schwartz Reviewed-by: Daniel Kiper --- hw/i386/multiboot.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/i386/multiboot.c b/hw/i386/multiboot.c index

[Qemu-devel] [PATCH QEMU v1 2/4] multiboot: Remove unused variables from multiboot.c

2017-12-21 Thread Jack Schwartz
Remove unused variables: mh_mode_type, mh_width, mh_height, mh_depth Signed-off-by: Jack Schwartz Reviewed-by: Daniel Kiper --- hw/i386/multiboot.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/hw/i386/multiboot.c b/hw/i386/multiboot.c index ff2733d..964feaf 100644 --- a/hw/i386

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