rs in PMCR follow the
> CPU
>
> On Wed, 18 May 2022 at 00:24, ishii.shuuic...@fujitsu.com
> wrote:
> >
> > Hi, Peter.
> >
> > > Shuuichirou, Itaru: this is another patch where we need to know
> > > an A64FX register value...
> >
> &
Hi, Peter.
> Shuuichirou, Itaru: this is another patch where we need to know
> an A64FX register value...
Sorry for the late reply.
The initial value of the pmcr_el0 register in A64FX is 0x46014040.
After applying this Peter's patch, should we submit a new patch as a64fx patch
from us?
or do y
Hi, Peter.
> Shuuichirou, Itaru: do either of you know the right setting for the A64FX for
> this? If
> you can find what the hardware value of the ICC_CTLR_EL3 or ICC_CTLR_EL1
> register is (more specifically, the PRIBits subfield) that should be enough
> to tell
> us.
The value of the PRIbits
> a64fx isn't the only CPU type the virt machine type supports which has
> EL2 support. In fact, all the CPU types supported by mach-virt do, unless
> KVM is enabled. So, while I understand the sentiment of this patch, it
> doesn't fit the current model. And, since we don't want to start
> accumula
> I already gave my r-b on the last posting, but here it is again
>
> Reviewed-by: Andrew Jones
Sorry, We overlooked that.
Thank you:)
Best regards,
> -Original Message-
> From: Andrew Jones
> Sent: Tuesday, August 31, 2021 7:20 PM
> To: Ishii, Shuuichirou/石井 周一郎
> Cc: peter.mayd...@
Thank you for your quick comments.
> Question: For testing, did you dump all the ID registers on this
> model and compare them with a dump of ID registers from real
> hardware? If so, that would be good info to put in the commit
> message or at least the cover letter.
Yes, it has been tested and
mayd...@linaro.org;
> phi...@redhat.com; qemu-devel@nongnu.org; qemu-...@nongnu.org
> Subject: Re: [PATCH v2 0/4] target/arm/cpu: Introduce sve_vq_supported bitmap
>
> On Fri, Aug 27, 2021 at 08:30:07AM +, ishii.shuuic...@fujitsu.com wrote:
> >
> > Thank you, Andre
ones ; richard.hender...@linaro.org;
> phi...@redhat.com; qemu-devel@nongnu.org; qemu-...@nongnu.org
> Subject: Re: [PATCH v2 0/4] target/arm/cpu: Introduce sve_vq_supported bitmap
>
> On Fri, 27 Aug 2021 at 09:30, ishii.shuuic...@fujitsu.com
> wrote:
> >
> >
> > Thank you
Thank you, Andrew, for creating the patches.
And thank you all for your comments.
I have applied the suggested v2 patch series by andrew locally,
and reviewed the next version of the a64fx patch series as follows.
I would appreciate if you could comment on whether there are
any problems with th
u-...@nongnu.org; qemu-devel@nongnu.org
> Subject: Re: [PATCH v4 1/3] target-arm: Add support for Fujitsu A64FX
>
> On Wed, Aug 18, 2021 at 08:29:15AM +, ishii.shuuic...@fujitsu.com wrote:
> >
> > We appreciate everyone's comments.
> > Before making the V5 patch, p
We appreciate everyone's comments.
Before making the V5 patch, please let me check the patch contents.
> This looks reasonable to me, but you also need the 'sve' property that states
> sve in
> supported at all.
> > > So maybe we should just go ahead and add all sve* properties,
In response t
> On Thu, 12 Aug 2021 at 10:25, Andrew Jones wrote:
> > On second thought, do we want the QMP CPU model expansion query to
> > show that this CPU type has sve,sve128,sve256,sve512? If so, then our
> > SVE work isn't complete, because we need those properties, set true by
> > default, but forbidd
inaro.org; qemu-...@nongnu.org; qemu-devel@nongnu.org
> Subject: Re: [PATCH v3 1/3] target-arm: cpu64: Add support for Fujitsu A64FX
>
> On Tue, Aug 10, 2021 at 08:23:39AM +, ishii.shuuic...@fujitsu.com wrote:
> >
> > Thanks for your comments.
> >
> > Before repost
Thanks for your comments.
Before reposting the fix patch series,
based on your comments and the v3 1/3 patch,
we have considered the following fixes.
If you have any comments on the fixes, please let us know.
---
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 9f0a5f84d5..84ebca731a 10
> I'm afraid this isn't the way a v2 patchseries should be structured.
> The idea is that a v2 series should be complete in itself, not based on
> whatever v1
> was. So when you make the changes requested in review of v1, you update the
> commits in your local git branch, and then you send out the
> This is confusing because I can't see this feature flag in the mainline
> branch. Have
> you inadvertently based this series from an internal branch?
I'm sorry for the confusion.
My lack of understanding of how to handle v2 patches has led me to create a v2
patch series
based on patches that
> This feature doesn't exist in upstream QEMU, so this won't apply.
> For a v2 of a patch, the patches should be based on upstream, not on top of
> the v1
> series.
Thank you for your comment.
I understood your point.
Best regards.
> -Original Message-
> From: Peter Maydell
> Sent: Fri
> Commit messages should describe what the patch is doing and why, so the reader
> can understand it without having to cross-reference old mailing list threads.
Thank you for your comment.
I understood your point.
Best regards.
> -Original Message-
> From: Peter Maydell
> Sent: Friday,
s.
> -Original Message-
> From: Peter Maydell
> Sent: Thursday, July 29, 2021 6:43 PM
> To: Ishii, Shuuichirou/石井 周一郎
> Cc: Thomas Huth ; Laurent Vivier ;
> Paolo Bonzini ; qemu-arm ;
> QEMU Developers
> Subject: Re: [PATCH 4/4] docs/system: Add a64fx(Fujitsu A64FX pr
PU_TYPE_NAME("a64fx"),
> };
Best regards.
> -----Original Message-
> From: Peter Maydell
> Sent: Monday, July 19, 2021 9:56 PM
> To: ishii.shuuic...@fujitsu.com
> Cc: Thomas Huth ; Laurent Vivier ;
> Paolo Bonzini ; qemu-arm ;
> QEMU Developers
> Subject: R
Hi Peter.
> These ones seem to have reached both qemu-devel and qemu-devel \o/
>
> https://lists.gnu.org/archive/html/qemu-devel/2021-07/msg06355.html
> https://lists.gnu.org/archive/html/qemu-arm/2021-07/msg00391.html
Thank you for contacting us.
Since our email seems to have successfully made
Test reply 2.
> -Original Message-
> From: Shuuichirou Ishii
> Sent: Monday, July 26, 2021 5:21 PM
> To: qemu-...@nongnu.org; qemu-devel@nongnu.org
> Subject: [PATCH v2] This is a test mail
>
> This is a test mail to check the behavior of my mail because it is not listed
> in the
> ML
Test reply.
> -Original Message-
> From: Shuuichirou Ishii
> Sent: Monday, July 26, 2021 5:21 PM
> To: qemu-...@nongnu.org; qemu-devel@nongnu.org
> Cc: Ishii, Shuuichirou/石井 周一郎
> Subject: [PATCH v2] This is a test mail
>
> This is a test mail to check the behavior of my mail because i
> To: Ishii, Shuuichirou/石井 周一郎 ; 'Peter Maydell'
>
> Cc: Laurent Vivier ; Thomas Huth ;
> QEMU Developers ; qemu-arm
> ; Paolo Bonzini
> Subject: Re: [PATCH 0/4] Add support for Fujitsu A64FX processor
>
> Hi Ishii,
>
> On 7/20/21 9:34 AM, ishii.shuuic...@fuj
> FWIW, this mail seems to have been accepted by the qemu-arm list:
> https://lists.gnu.org/archive/html/qemu-arm/2021-07/msg00341.html
> but it didn't get to the qemu-devel list.
Thank you for letting us know.
As you said, it seems that it is not listed in qemu-devel.
We are checking with the adm
Hi, peter
Thank you for your comment.
> Hi; it looks like something with your outgoing email setup still disagrees
> with QEMU's mailing list server :-( As far as I can tell these emails didn't
> make it to the list, so only people on the direct-cc list will have
> seen them :-(
As you said, it
Hi, peter.
Thank you for your comment.
> I think it would be worth scoping out how much work the a64fx CPU would
> require (ie what else does it need beyond these extensions and whatever
> features we currently implement?). If that's not a lot of work it might be
> simpler
> to just add it (poss
o: Ishii, Shuuichirou/石井 周一郎 ; Peter
> Maydell
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org
> Subject: Re: [RFC] Adding the A64FX's HPC funtions.
>
> On 6/3/21 1:17 AM, ishii.shuuic...@fujitsu.com wrote:
> > Hi, Richard.
> >
> > Thank you for your comment.
&g
Hi, Richard.
Thank you for your comment.
> My first thought is that -cpu max can simply enable the extensions, without
> extra flags. The max cpu has all of the features that we can enable, and as I
> see it this is just one more.
Let me confirm a few things about the above comment.
Does it mea
@nongnu.org; qemu-devel@nongnu.org
> Subject: Re: [RFC] Adding the A64FX's HPC funtions.
> Importance: High
>
> On Fri, 4 Jun 2021 at 09:29, ishii.shuuic...@fujitsu.com
> wrote:
> >
> > Hi, Richard.
> >
> > > Well, Peter disagreed with having them enab
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