Sean, understood with many thanks!
Good luck,
Harry
On Wed, Jul 28, 2021 at 3:01 PM Sean Christopherson wrote:
>
> On Wed, Jul 28, 2021, harry harry wrote:
> > Sean, sorry for the late reply. Thanks for your careful explanations.
> >
> > > For emulation of any instru
Sean, sorry for the late reply. Thanks for your careful explanations.
> For emulation of any instruction/flow that starts with a guest virtual
> address.
> On Intel CPUs, that includes quite literally any "full" instruction emulation,
> since KVM needs to translate CS:RIP to a guest physical addr
Hi Sean,
Thanks for the explanations. Please see my comments below. Thanks!
> When TDP (EPT) is used, the
> hardware MMU has two parts: the TDP PTEs that are controlled by KVM, and the
> IA32
> PTEs that are controlled by the guest. And there's still a KVM MMU for the
> guest;
> the KVM MMU i
Hi Sean,
> No, each vCPU has its own MMU instance, where an "MMU instance" is (mostly) a
> KVM
> construct. Per-vCPU MMU instances are necessary because each vCPU has its own
> relevant state, e.g. CR0, CR4, EFER, etc..., that affects the MMU instance in
> some way. E.g. the MMU instance is use
Dear Sean,
Thanks for the comments!
> Heh, because the MMUs are all per-vCPU, it actually wouldn't be that much
> effort
> beyond supporting !TDP and TDP for different VMs...
>
Sorry, may I know what do you mean by "MMUs are all per-vCPU"? Do you
mean the MMUs walk the page tables of each vCPU
Dear Maxim,
Thanks for your reply!
> For same VM, I don't think it is feasable.
>
> For multiple VMs make some use NPT/EPT and some don't,
> this should be possible to implement.
>
> Why do you need it?
>
I am just curious about it :).
Best,
Harry
other 40 cores use SPT). What do you think? Thanks!
Best regards,
Harry
On Mon, Jul 12, 2021 at 4:49 AM Maxim Levitsky wrote:
>
> On Sun, 2021-07-11 at 15:13 -0500, harry harry wrote:
> > Hi all,
> >
> > I hope you are very well! May I know whether it is possible to enable
Hi all,
I hope you are very well! May I know whether it is possible to enable
two-dimensional page translation (e.g., Intel EPT) mechanisms and
shadow page table mechanisms in Linux QEMU/KVM at the same time on a
physical server? For example, if the physical server has 80 cores, is
it possible to
Hi Maxim,
Thanks for your emphasis. It's much clearer.
Best,
Harry
Hi Paolo and Sean,
It is clear to me now. Thanks much for your reply and help.
Best regards,
Harry
Hi Sean,
Thanks much for your detailed replies. It's clear to me why GPAs are
different from HVAs in QEM/KVM. Thanks! I appreciate it if you could
help with the following two more questions.
On Tue, Oct 13, 2020 at 3:03 AM Sean Christopherson
wrote:
>
> This is where memslots come in. Think of
Hi Paolo and Sean,
Thanks much for your prompt replies and clear explanations.
On Tue, Oct 13, 2020 at 2:43 AM Paolo Bonzini wrote:
>
> No, the logic to find the HPA with a given HVA is the same as the
> hardware logic to translate HVA -> HPA. That is it uses the host
> "regular" page tables, n
BTW, I assume the software logic for KVM to find the HPA with a given HVA
(as you said like below) should be the same as the hardware logic in MMU
to translate ``GPA -> [extended/nested page tables] -> HPA''. If this is
true, I cannot understand how KVM can find a correct HPA with an HVA (e.g.,
ar
Hi Sean,
Thanks for the prompt reply. Please see my following reply. Thanks.
On Tue, Oct 13, 2020 at 12:52 AM Sean Christopherson <
sean.j.christopher...@intel.com> wrote:
>
> On Tue, Oct 13, 2020 at 12:30:39AM -0400, harry harry wrote:
> > Hi Sean,
> >
> > Thank y
BTW, I still have one more question as follows. Thanks!
On Mon, Oct 12, 2020 at 12:54 PM Sean Christopherson
wrote:
>
> No, the guest physical address spaces is not intrinsically tied to the host
> virtual address spaces. The fact that GPAs and HVAs are related in KVM is a
> property KVM's archi
Hi Sean,
Thank you very much for your thorough explanations. Please see my
inline replies as follows. Thanks!
On Mon, Oct 12, 2020 at 12:54 PM Sean Christopherson
wrote:
>
> No, the guest physical address spaces is not intrinsically tied to the host
> virtual address spaces. The fact that GPAs
Hi Maxim,
Thanks much for your reply.
On Sun, Oct 11, 2020 at 3:29 AM Maxim Levitsky wrote:
>
> On Sun, 2020-10-11 at 01:26 -0400, harry harry wrote:
> > Hi QEMU/KVM developers,
> >
> > I am sorry if my email disturbs you. I did an experiment and found the
> >
Hi QEMU/KVM developers,
I am sorry if my email disturbs you. I did an experiment and found the
guest physical addresses (GPAs) are not the same as the corresponding
host virtual addresses (HVAs). I am curious about why; I think they
should be the same. I am very appreciated if you can give some
co
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