rally aligned, so this fixes that
wrong behavior by raising address-misaligned exception if the address in rs1
is not naturally aligned.
Signed-off-by: Frederic Konrad
---
target/riscv/insn_trans/trans_rva.c.inc | 19 +++
1 file changed, 19 insertions(+)
diff --git a/target/ris
Now there is an option to enable misaligned accesses traps, check the alignment
during load and store for the RVI instructions. Do not generate them if the
zama16b extension is there.
Signed-off-by: Frederic Konrad
---
target/riscv/insn_trans/trans_rvi.c.inc | 7 +++
1 file changed, 7
misaligned access
happens.
Signed-off-by: Frederic Konrad
---
target/riscv/cpu.c | 5 +
target/riscv/cpu_cfg.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f219f0c3b5..1696d3db2a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
turally aligned even if
the store shouldn't happen.
Best Regards,
Fred
Frederic Konrad (3):
target/riscv: add a trap-misaligned-access property
target/riscv: generate misaligned access trap for rvi insn
target/riscv: fix the trap generation for conditional store
Hi,
Those are various simple fixes for ZynqMP:
* 1: fixes a possible out of bound access in the SPI model.
* 2: is a trivial fix for documentation url.
* 3: is a log guest error fix for the CSU DMA.
Best Regards,
Fred
Frederic Konrad (3):
hw/ssi/xilinx_spips: fix an out of bound access
out of s->regs[addr] in xilinx_spips_write for spips and qspips.
This fixes that wrong behavior.
Reviewed-by: Luc Michel
Signed-off-by: Frederic Konrad
---
hw/ssi/xilinx_spips.c | 7 ++-
include/hw/ssi/xilinx_spips.h | 3 +++
2 files changed, 9 insertions(+), 1 deletion(-)
d
It seems that the url changed a bit, and it triggers an error. Fix the URLs so
the documentation can be reached again.
Signed-off-by: Frederic Konrad
---
hw/dma/xlnx_csu_dma.c | 2 +-
include/hw/misc/xlnx-versal-cframe-reg.h | 2 +-
include/hw/misc/xlnx-versal-cfu.h
case.
While at it remove the comment marking the SIZE register as write-only.
See:
https://docs.xilinx.com/r/en-US/ug1087-zynq-ultrascale-registers/CSUDMA_SRC_SIZE-CSUDMA-Register
Signed-off-by: Frederic Konrad
---
hw/dma/xlnx_csu_dma.c | 12
1 file changed, 8 insertions(+), 4
c:
commit 58ac482a66de09a7590f705e53fc6a3fb8a055e8
Author: Frederic Konrad
Date: Tue Jun 14 15:59:15 2016 +0100
introduce xlnx-dp
This is the implementation of the DisplayPort.
It has an aux-bus to access dpcd and edid.
This commit has the following comment in it:
+static void xlnx_dp_audio_cal
Hi Gregg,
AFAIK the leon3-generic can emulate the GR712RC with some little differences in
the memorymap and / or timer / CPU count. (You should be able to boot the
Gaisler monocore linux with it).
About the SMP support AdaCore had a few patches for it, I'll let Fabien answer.
Regards,Fred
> -Original Message-
> From: Peter Maydell
> Sent: 06 June 2022 11:20
> To: Frederic Konrad
> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org;
> edgar.igles...@gmail.com; alist...@alistair23.me; Sai Pavan Boddu
> ; Edgar Iglesias ;
> fkon...@amd.com
> Subje
> -Original Message-
> From: Peter Maydell
> Sent: 23 May 2022 14:52
> To: Frederic Konrad
> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org;
> edgar.igles...@gmail.com; alist...@alistair23.me; Sai Pavan Boddu
> ; Edgar Iglesias ; Sai Pavan Boddu
> ; Edgar
oduce xlnx-dp")
Signed-off-by: Frederic Konrad
Reviewed-by: Edgar E. Iglesias
---
hw/display/xlnx_dp.c | 17 ++---
include/hw/display/xlnx_dp.h | 9 +++--
2 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c
i
From: Sai Pavan Boddu
Add a periodic timer which raises vblank at a frequency of 30Hz.
Signed-off-by: Sai Pavan Boddu
Signed-off-by: Edgar E. Iglesias
Changes by fkonrad:
- Switched to transaction-based ptimer API.
- Added the DP_INT_VBLNK_START macro.
Signed-off-by: Frederic Konrad
last patches.
Tested by booting Petalinux with the framebuffer enabled.
Best Regards,
Fred
v1 -> v2:
* Better use of the ptimer API by using a correct POLICY as suggested
by Peter Maydell (Patch 2).
* Rebased on 78ac2eeb.
Frederic Konrad (2):
xlnx_dp: fix the wrong register s
From: Sai Pavan Boddu
Fix interrupt disable logic. Mask value 1 indicates that interrupts are
disabled.
Signed-off-by: Sai Pavan Boddu
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Frederic Konrad
---
hw/display/xlnx_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
igned-off-by: Frederic Konrad
Reviewed-by: Edgar E. Iglesias
---
hw/arm/xlnx-zynqmp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 375309e68e..383e177a00 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -
> -Original Message-
> From: Peter Maydell
> Sent: 16 May 2022 10:57
> To: Frederic Konrad
> Cc: qemu-devel@nongnu.org; alist...@alistair23.me;
> edgar.igles...@gmail.com; qemu-...@nongnu.org; Sai Pavan Boddu
> ; Edgar Iglesias ;
> fkon...@amd.com; Sai Pava
.@alistair23.me; edgar.igles...@gmail.com;
> peter.mayd...@linaro.org; qemu-...@nongnu.org; Sai Pavan Boddu
> ; Edgar Iglesias ;
> fkon...@amd.com
> Subject: [PATCH v1 0/4] xlnx-zcu102: fix the display port.
>
> From: Frederic Konrad
>
> Hi,
>
> This patch set fixes so
@gmail.com; Francisco Eduardo Iglesias
> ; Sai Pavan Boddu ; Frederic
> Konrad ; Edgar Iglesias ;
> edgar.igles...@amd.com
> Subject: [PATCH v1 4/4] hw/arm: versal: Connect the CRL
>
> From: "Edgar E. Iglesias"
>
> Connect the CRL (Clock Reset LPD) to the Versal
@gmail.com; Francisco Eduardo Iglesias
> ; Sai Pavan Boddu ; Frederic
> Konrad ; Edgar Iglesias ;
> edgar.igles...@amd.com
> Subject: [PATCH v1 3/4] hw/misc: Add a model of the Xilinx Versal CRL
>
> From: "Edgar E. Iglesias"
>
> Add a model of the Xilinx Versal
Iglesias
; Sai Pavan Boddu ; Frederic Konrad
; Edgar Iglesias ; edgar.igles...@amd.com
Subject: [PATCH v1 2/4] hw/arm: versal: Add the Cortex-R5Fs
From: "Edgar E. Iglesias"
Add the Cortex-R5Fs of the Versal RPU (Real-time Processing Unit) subsystem.
Signed-off-by: Edgar E. Iglesias
-
Iglesias
; Sai Pavan Boddu ; Frederic Konrad
; Edgar Iglesias ; edgar.igles...@amd.com
Subject: [PATCH v1 1/4] hw/arm: versal: Create an APU CPU Cluster
From: "Edgar E. Iglesias"
Create an APU CPU Cluster. This is in preparation to add the RPU.
Signed-off-by: Edgar E. Iglesias
---
h
Le 4/7/22 à 12:32, Peter Maydell a écrit :
On Tue, 14 Jun 2016 at 15:40, Peter Maydell wrote:
From: KONRAD Frederic
This is the implementation of the DisplayPort.
It has an aux-bus to access dpcd and edid.
Graphic plane is connected to the channel 3.
Video plane is connected to the chann
frederic.kon...@adacore.com and kon...@adacore.com will stop working starting
2022-04-01.
Use my personal email instead.
Signed-off-by: Frederic Konrad
---
.mailmap| 3 ++-
MAINTAINERS | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/.mailmap b/.mailmap
index
o test.elf
$ qemu-system-avr -serial mon:stdio -nographic -no-reboot -M mega \
-bios test.elf
qemu-system-avr: Current machine: Arduino Mega (ATmega1280) with 'avr6' CPU
qemu-system-avr: ELF image 'test.elf' is for 'avr51' CPU
So this fixes the atmega1280
From: KONRAD Frederic
Currently "cf-core.xml" is sent to GDB when using any m68k flavor. Thing is
it uses the "org.gnu.gdb.coldfire.core" feature name and gdb 8.3 then expects
a coldfire FPU instead of the default m68881 FPU.
This is not OK because the m68881 floats registers are 96 bits wide s
Ping!
This is mostly reviewed maybe the 6th patch needs a little look.
Thanks,
Fred
On 04/28/2017 04:59 PM, fred.kon...@greensocs.com wrote:
> From: KONRAD Frederic
>
> This series allows to execute code from mmio areas.
> The main goal of this is to be able to run code for example from an SPI
Hi,
On 03/20/2017 07:00 PM, Anton Volkov wrote:
> Made functions *_exit in hw/ return void instead of int (they returned 0 all
> the time)
> and removed related return value checks
>
> Signed-off-by: Anton Volkov
> ---
> hw/audio/hda-codec.c | 3 +--
> hw/audio/intel-hda.c
On 03/06/2017 10:43 AM, Alex Bennée wrote:
>
> Frederic Konrad writes:
>
>> Hi All,
>>
>> I've a strangeness with the "drop iolock" patch.
>> It seems it has an impact on the MMIO execution patch-set I'm working
>> on:
>
> Hmm
Hi All,
I've a strangeness with the "drop iolock" patch.
It seems it has an impact on the MMIO execution patch-set I'm working
on:
Basically modifying the memory tree is causing a Bad Ram Address error.
I wonder if this can't happen with hotplug/unplug model as well.
I'll look into this.
Shoot i
On 03/02/2017 08:53 PM, Alex Bennée wrote:
> ..just like the rest of the displayed ESR register. Otherwise people
> might scratch their heads if a not obviously hex number is displayed
> for the EC field.
>
> Signed-off-by: Alex Bennée
> ---
> target/arm/helper.c | 2 +-
> 1 file changed, 1 inse
Hi Alex,
On 03/02/2017 08:53 PM, Alex Bennée wrote:
> While I was debugging the icount issues I realised a bunch of the
> messages look quite similar. I've fixed this by including __func__ in
> the debug print. At the same time I move the a modern if (GATE) style
> printf which ensures the compile
On 03/03/2017 02:44 PM, Edgar E. Iglesias wrote:
> On Fri, Feb 17, 2017 at 09:17:10PM +0100, fred.kon...@greensocs.com wrote:
>> From: KONRAD Frederic
>>
>> This introduces a special callback which allows to run code from some MMIO
>> devices.
>>
>> SysBusDevice with a MemoryRegion which implement
Hi All,
Any feedback for the 4 last patches?
Thanks,
Fred
On 02/17/2017 09:17 PM, fred.kon...@greensocs.com wrote:
> From: KONRAD Frederic
>
> This series allows to execute code from mmio areas.
> The main goal of this is to be able to run code for example from an SPI
> device.
>
> The three
On 02/23/2017 01:31 AM, Richard Henderson wrote:
> On 02/17/2017 01:30 AM, fred.kon...@greensocs.com wrote:
>> From: KONRAD Frederic
>>
>> get_page_addr_code(..) does a cpu_ldub_code to fill the tlb:
>> This can lead to some side effects if a device is mapped at this address.
>>
>> So this patch r
Hi Peter,
This won't be easy unfortunately, at least not clean :).
The vendor_id device_id are part of the PCIDeviceClass.
So I _think_ you can't use a qom parameter for that.
But... it seems that these fields are used firstly in
pci_qdev_realize (to be checked) so maybe it's okay to change them
l
On 02/16/2017 03:39 PM, Paolo Bonzini wrote:
>
>
> On 16/02/2017 15:30, fred.kon...@greensocs.com wrote:
>> From: KONRAD Frederic
>>
>> This series allows to execute code from mmio areas.
>> The main goal of this is to be able to run code for example from an SPI
>> device.
>>
>> The three first
On 02/16/2017 03:39 PM, Paolo Bonzini wrote:
>
>
> On 16/02/2017 15:30, fred.kon...@greensocs.com wrote:
>> From: KONRAD Frederic
>>
>> This series allows to execute code from mmio areas.
>> The main goal of this is to be able to run code for example from an SPI
>> device.
>>
>> The three first
Hi,
If I understand right:
You want to run a zynq qemu on a centos host?
On 02/09/2017 09:25 AM, Wojciech Zebrowski wrote:
> Hi
>
> I try connect my host linux centos USB to Qemu for Xilinx Zynq solution.
> I do following step :
> 1.Check usb vendor id , product id: lsusb
>
>
>
>
> *Bus 001
On 02/09/2017 09:53 PM, Bystricky, Juro wrote:
>
>
>> On 02/09/2017 07:52 PM, Juro Bystricky wrote:
>>> JTAG UART core eliminates the need for a separate RS-232 serial
>>> connection to a host PC for character I/O.
>>
>> And how does this describe the content of this patch ? This patch adds a
>>
Hi,
On 02/09/2017 07:52 PM, Juro Bystricky wrote:
> JTAG UART core eliminates the need for a separate RS-232 serial
> connection to a host PC for character I/O.
>
> Hardware emulation based on:
> https://www.altera.com/en_US/pdfs/literature/ug/ug_embedded_ip.pdf
> (Please see "Register Map" on pa
On 02/07/2017 02:53 PM, oussema ben khedher wrote:
> hi
> in my academic project i needed to know how qemu exactly translate an arm
> instruction to the host assembly (in my case x86) so if you can help me to
> know the function in the source code of qemu that tdo this work
> thank you
>
Hi,
On 02/07/2017 05:13 PM, Peter Maydell wrote:
> On 26 January 2017 at 09:47, wrote:
>> From: KONRAD Frederic
>>
>> This adds the qemu-clock documentation.
>>
>> Signed-off-by: KONRAD Frederic
>>
>> V1 -> V2:
>> * Fixed in accordance with the changes in the previous patches.
>> ---
>> docs/clo
On 02/04/2017 02:59 PM, Frederic Konrad wrote:
> On 02/04/2017 01:41 PM, Paolo Bonzini wrote:
>>
> ...
>>>
>>> Doesn't hotplug use dynamic MemoryRegion? In which case we better
>>> make that work with MTTCG. I wonder if we can't simply handle t
On 02/07/2017 10:31 AM, Cédric Le Goater wrote:
> On 02/07/2017 10:22 AM, Frederic Konrad wrote:
>>> I see how these routines are used in patch 10/10. But if we were
>>> open coding device CRF_APB, I don't think we would need them at
>>> all and it would make the
On 02/06/2017 04:58 PM, Cédric Le Goater wrote:
> Hello,
>
> On 01/26/2017 10:47 AM, fred.kon...@greensocs.com wrote:
>> From: KONRAD Frederic
>>
>> This introduces the clock binding and the update part.
>> When the qemu_clk_rate_update(qemu_clk, int) function is called:
>> * The clock callback
On 02/06/2017 03:20 PM, Cédric Le Goater wrote:
> On 01/26/2017 10:47 AM, fred.kon...@greensocs.com wrote:
>> From: KONRAD Frederic
>>
>> This allows to add a clock to a DeviceState.
>> Contrary to gpios, the clock pins are not contained in the DeviceState but
>> with the child property so they ca
nclude/qemu/qemu-clock.h b/include/qemu/qemu-clock.h
>> new file mode 100644
>> index 000..e7acd68
>> --- /dev/null
>> +++ b/include/qemu/qemu-clock.h
>> @@ -0,0 +1,40 @@
>> +/*
>> + * QEMU Clock
>> + *
>> + * Copyright (C) 2016 : GreenS
On 02/04/2017 02:17 PM, Peter Maydell wrote:
> On 4 February 2017 at 12:52, Frederic Konrad
> wrote:
>> Is that the case that we might get a Bad RAM address error or some such
>> if we are not on a page boundary (or too small as you say)?
>> I guess this is a limit
On 02/04/2017 01:41 PM, Paolo Bonzini wrote:
>
...
>>
>> Doesn't hotplug use dynamic MemoryRegion? In which case we better
>> make that work with MTTCG. I wonder if we can't simply handle that
>> with a safe_work for this case?
>
> Hot-unplug works because the backing memory is only freed when th
On 02/04/2017 01:33 PM, Peter Maydell wrote:
> On 3 February 2017 at 17:06, wrote:
>> From: KONRAD Frederic
>>
>> This patch-set allows to execute code from mmio areas.
>> The main goal of this is to be able to run code for example from an SPI
>> device.
>>
>> The three first patch fixes the wa
On 02/04/2017 12:30 PM, Edgar E. Iglesias wrote:
> On Fri, Feb 03, 2017 at 06:06:33PM +0100, fred.kon...@greensocs.com wrote:
>> From: KONRAD Frederic
>>
>> This replaces env1 and page_index variables by env and index
>> so we can use VICTIM_TLB_HIT macro later.
>>
>
> Hi Fred,
>
> A question, w
On 02/03/2017 06:26 PM, Paolo Bonzini wrote:
>
>
> On 03/02/2017 09:06, fred.kon...@greensocs.com wrote:
>> +host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size,
>> &offset);
>> +
>> +if (!host || !size) {
>> +memory_region_transaction_commit();
>> +return fals
Ping!
Thanks,
Fred
On 01/26/2017 10:47 AM, fred.kon...@greensocs.com wrote:
> From: KONRAD Frederic
>
> Hi,
>
> This is the second version of the clock framework API it contains:
>
> * The first 6 patches which introduce the framework.
> * The 7th patch which introduces a fixed-clock mode
On 01/09/2017 04:18 PM, Max Filippov wrote:
> Hello,
>
> I'm trying to reimplement xtensa CCOUNT (cycle counter) and
> CCOMPARE (CCOUNT-based timer interrupts) using QEMU
> timers. That is CCOUNT value is derived from the
> QEMU_CLOCK_VIRTUAL clock and CCOMPARE interrupts are
> generated from the
On 06/28/2016 09:30 PM, miny...@acm.org wrote:
> From: Corey Minyard
>
> Change 2293c27faddf (i2c: implement broadcast write) added broadcast
> capability to the I2C bus, but it broke SMBus read transactions.
> An SMBus read transaction does two i2c_start_transaction() calls
> without an interven
On 07/01/2016 02:45 PM, Peter Maydell wrote:
> On Windows 'aux.*' is a reserved name and cannot be used for
> filenames; see
>
> https://msdn.microsoft.com/en-gb/library/windows/desktop/aa365247(v=vs.85).aspx
>
> This prevents cloning the QEMU git repo on Windows:
>
> C:\Java\sources\kvm> git
Hi Alex,
We decided in Seattle to make this flag per tb (eg move it to the tb
struct).
On 24/02/2016 18:30, Alex Bennée wrote:
> Hi,
>
> So I've been working on reducing MTTCG tb_lock contention and currently
> have a tb_lock around the following code (in my cpu_exec):
>
> /* Note: we do it
On 08/01/2016 11:40, Peter Maydell wrote:
> On 8 January 2016 at 00:39, Alistair Francis
> wrote:
>> On Wed, Dec 16, 2015 at 8:33 AM, Alistair Francis
>> wrote:
>>> On Tue, Dec 15, 2015 at 1:56 PM, Peter Maydell
>>> wrote:
On 15 December 2015 at 20:52, Peter Crosthwaite
wrote:
>
On 19/01/2016 23:35, Alistair Francis wrote:
> From: Peter Crosthwaite
>
> An API similar to the existing qdev_get_gpio_in() except gets outputs.
> Useful for:
>
> 1: Implementing lightweight devices that don't want to keep pointers
> to their own GPIOs. They can get their GPIO pointers at runtime
Hi,
Is there a git tree with this series somewhere?
Looks nice.
Thanks,
Fred
On 14/01/2016 11:55, Peer Adelt wrote:
> Hey guys :)
>
> We have developed a generic concept to annotate TranslationBlocks during
> runtime. The initial idea was to use it for time annotation with data from
> static ana
On 02/11/2015 10:09, Frederic Konrad wrote:
> On 19/10/2015 06:09, Peter Crosthwaite wrote:
>> Most of the control flow logic between send and recv (error checking
>> etc) is the same. Factor this out into a common send_recv() API.
>> This is then usable by clients, where
On 16/01/2016 02:50, Alistair Francis wrote:
> On Mon, Jan 4, 2016 at 10:25 AM, wrote:
>> From: KONRAD Frederic
>>
>> This adds the DP and the DPDMA to the Zynq MP platform.
>>
>> Signed-off-by: KONRAD Frederic
>> Reviewed-by: Peter Crosthwaite
>> Tested-By: Hyun Kwon
>> ---
>> hw/arm/xlnx-z
display/xlnx_dp.c
>> @@ -0,0 +1,1361 @@
>> +/*
>> + * xlnx_dp.c
>> + *
>> + * Copyright (C) 2015 : GreenSocs Ltd
>> + * http://www.greensocs.com/ , email: i...@greensocs.com
>> + *
>> + * Developed by :
>> + * Frederic Konrad
>> +
On 16/01/2016 01:33, Alistair Francis wrote:
> On Mon, Jan 4, 2016 at 10:25 AM, wrote:
>> From: KONRAD Frederic
>>
>> This is the 6th version of this patch-set of the implementation of the Xilinx
>> DisplayPort and DPDMA.
>>
>> This 6th version fixes some minors issues.
>>
>> Second patch introd
- /dev/null
>> +++ b/hw/display/xlnx_dp.c
>> @@ -0,0 +1,1370 @@
>> +/*
>> + * xlnx_dp.c
>> + *
>> + * Copyright (C) 2015 : GreenSocs Ltd
>> + * http://www.greensocs.com/ , email: i...@greensocs.com
>> + *
>> + * Developed by :
>> + *
On 24/11/2015 04:42, Alistair Francis wrote:
> On Mon, Nov 23, 2015 at 6:53 PM, KONRAD Frederic
> wrote:
>>
>> Le 20/11/2015 13:21, Alistair Francis a écrit :
>>> On Fri, Oct 16, 2015 at 7:11 PM, wrote:
From: KONRAD Frederic
This adds the DP and the DPDMA to the Zynq MP platform.
On 19/10/2015 06:09, Peter Crosthwaite wrote:
> Most of the control flow logic between send and recv (error checking
> etc) is the same. Factor this out into a common send_recv() API.
> This is then usable by clients, where the control logic for send
> and receive differs only by a boolean. E.g.
>
ONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
>>
>> obj-$(CONFIG_PVPANIC) += pvpanic.o
>> obj-$(CONFIG_EDU) += edu.o
>> +obj-$(CONFIG_AUX) += aux.o
>> diff --git a/hw/misc/aux.c b/hw/misc/aux.c
>> new file mode 100644
>> index 000..bf300f7
>>
On 29/10/2015 03:00, Peter Crosthwaite wrote:
> On Wed, Oct 28, 2015 at 10:32 AM, Alistair Francis <
> alistair.fran...@xilinx.com> wrote:
>
>> Connect the Xilinx SPI device to the ZynqMP model.
>>
>>
> "devices"
>
>
>> Signed-off-by: Alistair Francis
>> ---
>> V3:
>> - Expose the SPI Bus as part
On 16/10/2015 23:57, Alistair Francis wrote:
> On Fri, Oct 16, 2015 at 6:41 AM, wrote:
>> From: KONRAD Frederic
>>
>> This is the fifth version of this patch-set of the implementation of the
>> Xilinx
>> DisplayPort and DPDMA.
>>
>> This fifth version moves some headers files to the right direc
Hi Claudio,
I'll rebase soon tomorrow with a bit of luck ;).
Thanks,
Fred
On 07/10/2015 14:46, Claudio Fontana wrote:
> Hello Frederic,
>
> On 11.08.2015 08:27, Frederic Konrad wrote:
>> On 11/08/2015 08:15, Benjamin Herrenschmidt wrote:
>>> On Mon, 2015-0
/dpcd.c
@@ -0,0 +1,171 @@
+/*
+ * dpcd.c
+ *
+ * Copyright (C) 2015 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: i...@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of
new file mode 100644
index 000..2dc2ac8
--- /dev/null
+++ b/hw/misc/aux.c
@@ -0,0 +1,374 @@
+/*
+ * aux.c
+ *
+ * Copyright 2015 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: i...@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad
+ *
+ * This program is free software
On 01/09/2015 22:58, Alistair Francis wrote:
On Tue, Jul 21, 2015 at 10:17 AM, wrote:
From: KONRAD Frederic
Seems this field is not needed.
The commit message should be updated to represent the patch.
Hmmm what do you mean?
It's not precise?
Thanks,
Fred
Signed-off-by: KONRAD Frederic
On 04/09/2015 01:34, Alistair Francis wrote:
On Thu, Sep 3, 2015 at 12:28 AM, Frederic Konrad
wrote:
On 02/09/2015 23:39, Alistair Francis wrote:
On Tue, Jul 21, 2015 at 10:17 AM, wrote:
From: KONRAD Frederic
This is the implementation of the DPDMA.
Signed-off-by: KONRAD Frederic
Hi Alex,
On 04/09/2015 09:49, Alex Bennée wrote:
Hi,
At KVM Forum I sat down with Paolo and Frederic and we came up with the
current outstanding tasks on MTTCG. This is not comprehensive but
hopefully covers the big areas. They are sorted in rough order we'd like
to get them up-streamed.
* lin
return;
+}
+
+assert(channel <= 5);
+s->data[channel] = p;
+}
+
+void xlnx_dpdma_trigger_vsync_irq(XlnxDPDMAState *s)
+{
+s->registers[DPDMA_ISR] |= (1 << 27);
+xlnx_dpdma_update_irq(s);
+}
+
+type_init(xlnx_dpdma_register_types)
diff --git a/hw
On 28/08/2015 16:49, Peter Maydell wrote:
On 12 August 2015 at 17:40, Paolo Bonzini wrote:
From: KONRAD Frederic
spinlock is only used in two cases:
* cpu-exec.c: to protect TranslationBlock
* mem_helper.c: for lock helper in target-i386 (which seems broken).
It's a pthread_mutex_t in
Hi everybody,
I'm trying to do the next version of the MTTCG work:
I would like to rebase on Alvise atomic instruction branch:
- Alvise can you rebase it on the 2.4.0 version without MTTCG support
and then
point me to the MTTCG specific changes so I can include them in my
tree?
I will a
On 12/08/2015 18:40, Paolo Bonzini wrote:
Hi, this is my attempt at 1) extracting upstreamable parts out of Fred's
MTTCG,
Can you take this one as well after the replace spinlock by QemuMutex:
"remove unused spinlock."
Thanks,
Fred
and 2) documenting what's going on in user-mode MTTCG 3) fi
On 12/08/2015 20:20, Alex Bennée wrote:
Frederic Konrad writes:
On 10/08/2015 17:27, fred.kon...@greensocs.com wrote:
From: KONRAD Frederic
This protects TBContext with tb_lock to make tb_* thread safe.
We can still have issue with tb_flush in case of multithread TCG:
An other CPU can
On 13/08/2015 16:58, Paolo Bonzini wrote:
On 13/08/2015 16:41, Frederic Konrad wrote:
One issue here is that when tcg_cpu_exec returns EXCP_HALTED, the
function keeps looping. There is no need to set cpu->exit_request in
that case, since in fact there is no request pending, so the while l
On 13/08/2015 13:17, Paolo Bonzini wrote:
On 10/08/2015 17:27, fred.kon...@greensocs.com wrote:
+while (!cpu->exit_request) {
qemu_clock_enable(QEMU_CLOCK_VIRTUAL,
(cpu->singlestep_enabled & SSTEP_NOTIMER) == 0);
@@ -1507,7 +1480,7 @@ static void tcg
On 13/08/2015 14:59, Paolo Bonzini wrote:
On 13/08/2015 14:51, Frederic Konrad wrote:
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 77bbff2..56b1f4d 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -285,7 +285,10 @@ struct CPUState {
void *env_ptr; /* CPUArchState
On 13/08/2015 15:12, Paolo Bonzini wrote:
On 13/08/2015 14:17, Frederic Konrad wrote:
diff --git a/linux-user/main.c b/linux-user/main.c
index fdee981..fd06ce9 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -107,7 +107,7 @@ static int pending_cpus;
/* Make sure everything is in a
On 13/08/2015 15:08, Paolo Bonzini wrote:
On 13/08/2015 15:05, Frederic Konrad wrote:
This removes tcg_halt_cond global variable.
We need one QemuCond per virtual cpu for multithread TCG.
Signed-off-by: KONRAD Frederic
Message-Id: <1439220437-23957-9-git-send-email-fred.kon...@greensocs.
On 12/08/2015 18:40, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini
---
cpu-exec.c | 6 ++
1 file changed, 6 insertions(+)
What about the icount part in CPUState and the tb_start/end ?
Can't this be removed as well?
Fred
diff --git a/cpu-exec.c b/cpu-exec.c
index 599e64d..bde5fd1 1
On 12/08/2015 18:40, Paolo Bonzini wrote:
From: KONRAD Frederic
This removes tcg_halt_cond global variable.
We need one QemuCond per virtual cpu for multithread TCG.
Signed-off-by: KONRAD Frederic
Message-Id: <1439220437-23957-9-git-send-email-fred.kon...@greensocs.com>
[Keep tcg_halt_cond fo
On 13/08/2015 15:01, Paolo Bonzini wrote:
+tb_lock();
tb = tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
max_cycles | CF_NOCACHE);
tb_gen_code() calls tb_alloc() which calls tb_flush() we end in a double
tb_lock here.
But that's probably not r
On 12/08/2015 18:41, Paolo Bonzini wrote:
From: KONRAD Frederic
This protects TBContext with tb_lock to make tb_* thread safe.
We can still have issue with tb_flush in case of multithread TCG:
another CPU can be executing code during a flush.
This can be fixed later by making all other TCG th
On 12/08/2015 18:41, Paolo Bonzini wrote:
softmmu requires more functions to be thread-safe, because translation
blocks can be invalidated from e.g. notdirty callbacks. Probably the
same holds for user-mode emulation, it's just that no one has ever
tried to produce a coherent locking there.
Thi
On 12/08/2015 18:40, Paolo Bonzini wrote:
From: KONRAD Frederic
spinlock is only used in two cases:
* cpu-exec.c: to protect TranslationBlock
* mem_helper.c: for lock helper in target-i386 (which seems broken).
It's a pthread_mutex_t in user-mode so better using QemuMutex directly in thi
On 10/08/2015 17:27, fred.kon...@greensocs.com wrote:
From: KONRAD Frederic
This protects TBContext with tb_lock to make tb_* thread safe.
We can still have issue with tb_flush in case of multithread TCG:
An other CPU can be executing code during a flush.
This can be fixed later by making
On 11/08/2015 15:59, Frederic Konrad wrote:
On 11/08/2015 14:45, Paolo Bonzini wrote:
On 10/08/2015 17:26, fred.kon...@greensocs.com wrote:
From: KONRAD Frederic
This is the 7th round of the MTTCG patch series.
Thanks to look at this.
Here is a list of issues that I found:
- tb_lock usage
On 12/08/2015 16:09, Paolo Bonzini wrote:
On 10/08/2015 17:27, fred.kon...@greensocs.com wrote:
From: KONRAD Frederic
tb_flush is not thread safe we definitely need to exit VCPUs to do that.
This introduces tb_flush_safe which just creates an async safe work which will
do a tb_flush later.
S
On 12/08/2015 11:58, Paolo Bonzini wrote:
On 11/08/2015 23:34, Frederic Konrad wrote:
Also if qemu_cond_broadcast(&qemu_io_proceeded_cond) is being dropped
there is no point keeping the guff around in qemu_tcg_wait_io_event.
Yes good point.
BTW this leads to high consumption of host CP
On 11/08/2015 22:12, Alex Bennée wrote:
Paolo Bonzini writes:
On 10/08/2015 17:27, fred.kon...@greensocs.com wrote:
void qemu_mutex_lock_iothread(void)
{
-atomic_inc(&iothread_requesting_mutex);
-/* In the simple case there is no need to bump the VCPU thread out of
- * TCG cod
On 11/08/2015 14:45, Paolo Bonzini wrote:
On 10/08/2015 17:26, fred.kon...@greensocs.com wrote:
From: KONRAD Frederic
This is the 7th round of the MTTCG patch series.
Thanks to look at this.
Here is a list of issues that I found:
- tb_lock usage in tb_find_fast is complicated and introduces
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